perm filename FACIL.TED[H,DOC] blob
sn#864522 filedate 1980-06-05 generic text, type C, neo UTF8
COMMENT ⊗ VALID 00090 PAGES
C REC PAGE DESCRIPTION
C00001 00001
C00009 00002 Stanford Artificial Intelligence Project May 12, 1973
C00011 00003 TABLE OF CONTENTS
C00013 00004 INTRODUCTION SECTION 1
C00015 00005 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00020 00006 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00024 00007 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00027 00008 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00031 00009 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00033 00010 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00041 00011 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00045 00012 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00047 00013 PDP-10 / PDP-6 DIFFERENCES SECTION 2
C00049 00014 SUMMARY OF I/O DEVICES SECTION 3
C00054 00015 SUMMARY OF I/O DEVICES SECTION 3
C00056 00016 USING MACHINE INPUT-OUTPUT INSTRUCTIONS SECTION 4
C00060 00017 USING MACHINE INPUT-OUTPUT INSTRUCTIONS SECTION 4
C00063 00018 III DISPLAY PROCESSOR SECTION 5
C00065 00019 III DISPLAY PROCESSOR SECTION 5
C00068 00020 III DISPLAY PROCESSOR SECTION 5
C00071 00021 III DISPLAY PROCESSOR SECTION 5
C00074 00022 III DISPLAY PROCESSOR SECTION 5
C00077 00023 III DISPLAY PROCESSOR SECTION 5
C00080 00024 III DISPLAY PROCESSOR SECTION 5
C00083 00025 III DISPLAY PROCESSOR SECTION 5
C00084 00026 III DISPLAY PROCESSOR SECTION 5
C00087 00027 III DISPLAY PROCESSOR SECTION 5
C00090 00028 * III DISPLAY PROCESSOR KEYBOARD SCANNER SECTION 5
C00093 00029 DATA DISC OPERATION MANUAL SECTION 6
C00097 00030 DATA DISC OPERATION MANUAL SECTION 6
C00100 00031 DATA DISC OPERATION MANUAL SECTION 6
C00110 00032 DATA DISC OPERATION MANUAL SECTION 6
C00116 00033 VIDEO SWITCH SECTION 7
C00119 00034 * KEYBOARD SCANNER OPERATION MANUAL SECTION 8
C00122 00035 * KEYBOARD SCANNER OPERATION MANUAL SECTION 8
C00125 00036 167 HIGH SPEED CHANNEL SECTION 9
C00127 00037 * LIBRASCOPE DISK FILE SECTION 10
C00134 00038 TELEVISION CAMERA INTERFACE SECTION 11
C00137 00039 * TELEVISION PAN, TILT, AND FOCUS SECTION 11.1
C00140 00040 * TELEVISION COLOR WHEEL AND TURRET POSITION SECTION 11.2
C00143 00041 * HAND-EYE TABLE TURNTABLE SECTION 11.3
C00146 00042 * LASER MIRROR CONTROL SECTION 11.4
C00148 00043 * STANFORD ELECTRIC ARM SECTION 13
C00150 00044 * STANFORD ELECTRIC ARM SECTION 13
C00155 00045 * THE ANALOG TO DIGITAL CONVERTER AND MULTIPLEXER SECTION 14
C00156 00046 * THE DIGITAL TO ANALOG CONVERTER SECTION 15
C00159 00047 * ELECTRONIC CLOCK SECTION 16
C00161 00048 * ELECTRONIC CLOCK SECTION 16
C00164 00049 XEROX GRAPHICS PRINTER SECTION 17
C00166 00050 XEROX GRAPHICS PRINTER SECTION 17
C00167 00051 XEROX GRAPHICS PRINTER SECTION 17
C00168 00052 XEROX GRAPHICS PRINTER SECTION 17
C00169 00053 XEROX GRAPHICS PRINTER SECTION 17
C00171 00054 XEROX GRAPHICS PRINTER SECTION 17
C00173 00055 XEROX GRAPHICS PRINTER SECTION 17
C00174 00056 XEROX GRAPHICS PRINTER SECTION 17
C00176 00057 XEROX GRAPHICS PRINTER SECTION 17
C00178 00058 XEROX GRAPHICS PRINTER SECTION 17
C00181 00059 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00183 00060 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00184 00061 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00185 00062 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00186 00063 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00187 00064 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00189 00065 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00196 00066 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00200 00067 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00204 00068 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00206 00069 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00209 00070 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00212 00071 * IBM BLOCK MULTIPLEX CHANNEL SECTION 18
C00222 00072 * TELEPHONE PAGING SYSTEM KLUDGE SECTION 19
C00224 00073 * VODER INTERFACE SECTION 20
C00227 00074 * VODER INTERFACE SECTION 20
C00229 00075 * VODER INTERFACE SECTION 20
C00236 00076 AUTO DIALER SECTION 21
C00238 00077 AUTO DIALER SECTION 21
C00239 00078 AUTO DIALER SECTION 21
C00242 00079 PDP-10 TO PDP-11 INTERFACE SECTION 22
C00244 00080 PDP-10 TO PDP-11 INTERFACE SECTION 22
C00247 00081 PDP-10 TO PDP-11 INTERFACE SECTION 22
C00250 00082 PDP-10 TO PDP-11 INTERFACE SECTION 22
C00253 00083 PDP-10 TO PDP-11 INTERFACE SECTION 22
C00256 00084 RESETTING THE WORLD SECTION 23
C00264 00085 RESETTING THE WORLD SECTION 23
C00267 00086 RESETTING THE WORLD SECTION 23
C00270 00087 RESETTING THE WORLD SECTION 23
C00272 00088 RESETTING THE WORLD SECTION 23
C00275 00089 RELOADING THE SYSTEM SECTION 24
C00282 00090
C00284 ENDMK
C⊗;
Stanford Artificial Intelligence Project May 12, 1973
Operating Note 56
FACILITY MANUAL
by
Ted Panofsky
ABSTRACT: This manual describes the operation of the
hardware devices now in service at the Stanford A-I Project. It
includes instruction formats for all user programmable I-O devices
and some other devices which are not written up accurately anywhere
else. This manual supercedes SAILON's 24, 25 and 26.
This work was supported in part by the Advanced Research Projects
Agency of the Department of Defense under Contract SD-183.
TABLE OF CONTENTS
1 INTRODUCTION
2 DIFFERENCES BETWEEN THE PDP-10 AND THE PDP-6
3 INPUT-OUTPUT DEVICE SUMMARY
4 USING MACHINE INPUT-OUTPUT INSTRUCTIONS
5 THE III DISPLAY PROCESSOR
6 THE DATA DISC DISPLAY SYSTEM
7 THE VIDEO SWITCH
8 THE MICROSWITCH KEYBOARD SCANNER
9 167 HIGH SPEED DATA CHANNEL
10 LIBRASCOPE DISK FILE
11 TELEVISION CAMERA INTERFACE
12 SPECIAL VISION HARDWARE
12.1 TELEVISION PAN, TILT, AND FOCUS
12.2 TELEVISION COLOR WHEEL AND TURRET POSITION
12.3 HAND-EYE TABLE TURNTABLE
12.4 LASER MIRROR CONTROL
13 STANFORD ELECTRIC ARM
******* 14 THE ANALOG TO DIGITAL CONVERTER AND MULTIPLEXER
15 THE DIGITAL TO ANALOG CONVERTER
16 AUDIO SYSTEM
******* 16.1 AUDIO OUTPUT SYSTEM
16.2 SPEECH PREPROCESSOR
16.3 REMOTE OPERATION OF THE AMPEX TAPE RECORDER
17 THE ELECTRONIC CLOCK
18 XEROX GRAPHICS PRINTER
19 2314 INTERFACE
20 TELEPHONE PAGING KLUGE
21 VODER INTERFACE
22 RESETTING THE WORLD
23 AUTO DIALER
24 RELOADING THE SYSTEM
INTRODUCTION SECTION 1
This manual describes the various hardware devices at the
Stanford Artificial Intelligence Project. It includes information
about most of the input/output devices on the system and their i/o
commands. Modifications and differences between the central
processors, a DEC KA-10 (PDP-10) and a DEC 166 (PDP-6), are
described here.
Some of the i/o devices described here are handled by
special UUO's described in the UUO chapter of the Monitor Manual.
The instructions described in this manual can be found in
their general forms in the DEC System-10 Reference Manual published
by Digital Equipment Corporation.
Any publication of this nature is doomed to nearly instant
obsolescence as new hardware is added, and obsolete devices
removed. This manual is kept on-line as HM[H,DOC]. Obsolete
writeups are kept in OLD[H,DOC].
PDP-10 / PDP-6 DIFFERENCES SECTION 2
The PDP-10 and the PDP-6 are not entirely program
compatible. However, the differences between the two machines,
except the floating point instructions, are very minor. The
following list is as complete as possible. This section supercedes
SAILON No.47 and No.47 Supplement 1.
FLOATING POINT INSTRUCTIONS
The instruction additions and changes on the PDP-10 were
designed with the specific intention of facilitating double precision
floating point calculation and cleaning up the operation of the PDP-6
arithmetic instructions.
1. The PDP-6 does not have the UFA (130) and DFN (131)
instructions.
2. The low order word of the FxxL instructions is different on
the two machines.
3. The PDP-10 FxxRI instructions are FxxRL on the PDP-6.
4. The PDP-6 does not have the divide check, floating overflow,
and floating exponent underflow flags. On the PDP-6, the floating
overflow flag is replaced with the PC change flag.
5. Rounding of FxxR instructions is handled in a different way
on the PDP-6. When the PDP-6 rounds a negative number whose
low-order part is exactly one-half, the round occurs toward zero. On
the PDP-10, one-half is rounded to give the more negative result.
6. Any floating add, subtract, or multiply instruction in which
the only significant bits of the answer are in the low-order word
before normalizing, produces a normalized non-zero result on the
PDP-10. On the PDP-6, the bits are lost.
PROCESSOR FLAGS
1. The PDP-6 PC change flag replaces the floating overflow flag
in the PDP-6 status word, PC word, and the JFCL instruction.
2. The PDP-6 does not have a divide check flag or a floating
exponent underflow flag.
3. Bit 7 of the PDP-10 PC flags word is used to store the state of a
flip flop named CALL FROM MONITOR. This bit is saved and restored in
the ame fashion as the other PC flag bits. It is cleared by MR
START, and set whenever an EX JSYS (effective address < 1000) is
executed in EXEC mode. This bit indicates to the called JSYS routine
that effective addresses, byte pointers, and BLT pointers passed as
arguments should refer to the EXEC mode address space, not the
current USER address space. When this bit is on, special XCT and
UMOVEx references are automatically forced into the EXEC mode address
space instead of the USER's space.
This feature simplifies the coding of EX JSYS routines which
accept pointers as arguments and which may be called either from USER
mode or EXEC mode. The routine merely makes use of any pointers with
UMOVE, or special XCT instructions, and the CALL FM MON flag
automatically forces references into the correct address space.
4. The CPU and PI status bits are slightly different. (see
Status Register section)
PDP-10 / PDP-6 DIFFERENCES SECTION 2
ADDRESS SWITCHES AND CONDITIONS
1. The address switches on the PDP-6 are compared with the
unrelocated address rather than the relocated address.
2. The PDP-6 has been modified to have address condition
switches like those on the PDP-10. These switches are located in
166 bay 1.
3. The PDP-6 lacks the Address Break feature.
4. The KA10 has been modified by the addition of two mode
switches (located in bay 2). These are denoted OLD/NEW and
USER/EXEC. In OLD mode, the USER/EXEC switch is ignore. AS=RLA is
generated from AS=MA. In NEW mode, the AS=RLA is requires both AS=MA
and the state of user mode addressing (i.e., EX REL A) must
correspond to the USER/EXEC switch.
PDP-6 EXTRA MEMORY REFERENCES
The PDP-6 makes some unnecessary memory references that the PDP-10
does not make. For example:
SETZ AC,-1
PDP-6. Location 777777 is fetched from memory which may result in
a protection violation or a non-ex mem.
PDP-10. Location 777777 is not fetched.
The SKIPx instructions on the PDP-6 have been fixed to avoid
redundant AC stores.
BYTE INCREMENT (IBP, ILDB and IDPB)
1. PDP-6
If a carry from the address field into the index register field
occurs while incrementing the byte pointer, the new index register is
used for the effective address calculation of the byte pointer.
2. PDP-10
If the same carry occurs on the PDP-10, the old index field is used
for the effective address calculation unless an interrupt occurs
after the byte pointer is incremented and before the LDB or DPB is
started. In this case, the new index field is used and the result
is identical to that on the PDP-6. Since the results in this case
are likely to be unpredictable, one might be cautious in using this
feature.
3. The PDP-6 has been modified so that an IBP instruction with
a non-zero AC field will load the AC with the (incremented) byte
pointer.
PDP-10 / PDP-6 DIFFERENCES SECTION 2
STORE CYCLE DIFFERENCES
The PDP-6 stores the results of any instruction in the order: memory,
AC1, AC2. The PDP-10 stores the results in the order: AC1, memory,
AC2. Two instructions behave slightly differently as a result.
POP AC, AC
a. PDP-6: (AC)-1000001→AC
b. PDP-10: ((AC)r)→AC
BLT when:
a. Loading the AC's over the BLT pointer,and
b. An interrupt occurs,and
c. The memory word being transfered is being written over
the pointer AC,and
d. The BLT still has more transfers to go.
On the PDP-6 the pointer word is written over the
memory word. The instruction can reasonably continue with
the updated pointer. On the PDP-10 the updated pointer is
destroyed by the memory word. When the instruction
continues, the result is a BLT using the memory word as a
pointer. The difference is only in the magnitude of the
loss. Reasonable programming won't be bothered with this.
DIFFERENCES IN THE SUBTRACT ALGORITHM
PDP-6:
Ones complement the AC, 2's complement add, ones complement
the result (3 steps).
PDP-10:
Direct 2's complement subtract (1 step).
The difference results in the CRY0 and CRY1 flags on the
PDP-6 being the complement of the results for the same
subtraction on the PDP-10. For example, say SUBI 1,105 on
the PDP-6 resulted in the CRY0 and CRY1 flags being 1 and 0
respectively; The PDP-10 would set the flags to 0 and 1.
(This assumes that both were 0 initially.)
PDP-10 / PDP-6 DIFFERENCES SECTION 2
PRIORITY INTERRUPTS
The PDP-6 may only have a JSR in the interrupt locations in order to
call an interrupt routine and enter executive mode. The PDP-10 may
have a JSR, PUSHJ, or JSP. Only these instructions store PC flags so
if some other instruction were used the processor would not enter
EXEC mode, and making a correct return from the interrupt would be
impossible.
The PDP-6 allows interrupts to occur at two places in an instruction:
Prior to the instruction fetch and in the effective address
calculation loop. The PDP-10 allows interrupts only in the effective
address calculation loop.
This difference shows up when the PC exceeds memory
bound for a user-mode program and an illegal memory
reference occurs. If the interrupt program recognizes the
illegal memory reference, turns off the illegal memory
reference flag, and tries to get out of the APR channel
quickly by requesting an interrupt on a lower priority
channel and dismissing the APR interrupt to the PC word
(unmodified from the time of the interrupt), the result is:
PDP-6: Everything works fine because the interrupt on the
lower priority channel is recognized prior to the
instruction fetch.
PDP-10: Another illegal memory reference interrupt results
because the instruction fetch (using the
out-of-bounds PC) occurs before the interrupt on
the lower priority channel is recognized.
When the PDP-6 makes an illegal memory reference from a user-mode
program it restarts at the beginning of the instruction timing chain.
The PDP-10 restarts in the instruction chain after the place where a
instruction is normally fetched, resulting in a 0 instruction. Also,
the interrupt system has not set up to trap the illegal memory
reference during the effective address calculation for the 0
instruction. The result of all this is:
PDP-6: The illegal memory reference flag interrupt occurs
before the beginning of the next instruction.
PDP-10: Executive location 40 has a 0 written into it (the 0
instruction results in a UUO which is dumped into executive
location 40). The interrupt occurs during the effective
address calculation for the instruction in executive
location 41.
PDP-10 / PDP-6 DIFFERENCES SECTION 2
UUO's AND UNIMPLEMENTED INSTRUCTIONS
PDP-6
a. UUO's 040-077 trap to executive locations 40
and 41.
b. UUO`s 000-037 trap to user locations 40 and 41 if in
user mode. If in exec mode, they trap to executive locations
40 and 41. (Note that 000 is considered a legal user UUO.)
c. Unimplemented instructions 100-117, 131, and 243,
when executed, have no effect (no-op).
PDP-10
(The PDP-10 is usually operated in MA TRAP OFFSET mode. This
moves the EXEC trap locations from 40-61 to 140-161.)
a. UUO`s 000 and 040-77 trap to executive locations 140
and 141.
b. UUO`s 001-037 trap to user locations 40 and 41 if in
user mode. If in exec mode, they trap to executive locations
140 and 141.
c. Any unimplemented instruction from 100-177 traps to
executive locations 160 and 161.
d. Unimplemented instruction 257 results in no
operation.
PDP-10 / PDP-6 DIFFERENCES SECTION 2
NEW INSTRUCTIONS
UMOVEx
The UMOVEx class of instruction modifications forces MOVEs to
and from USER space.
____________________________________________________________
|0 6|7 8|9 12| 13 |14 17|18 35|
| 100 | M | A | I | X | Y |
|_____|___|____|____|_____|__________________________________|
Move one word from the source to the destination specified by
M, using the protection/relocation registers or the user address map
if mapping is enabled. The source is unaffected, the original
contents of the destination are lost.
UMOVE User move 100
UMOVEI User move immediate 101
UMOVEM User move to memory 102
UMOVES User move to self 103
These instructions provide a convenient way for the monitor to invoke
the USER address mapping to fetch or store information into the USER
address space (UMOVE or UMOVEM). UMOVEI provides a way for the
monitor to do address computation using indirect addressing through
the USER address space. Of course, indexing and AC references are not
affected by the choice of USER map/EXEC map. However, addresses
which indirect through the USER ACs are handled specially (see
section on Call From Monitor Flag).
JSYS Jump to system
____________________________________________________________
|0 8|9 12| 13 |14 17|18 35|
| 104 | A | I | X | Y |
|_________|____|____|_____|__________________________________|
If the effective address is 1000 or greater, fetch a double
(left half, right half) pointer from the effective address. Store the
flags and incremented PC in the location indicated by the left half
pointer and jump to the location indicated by the right half pointer.
The flags and PC are stored in the left and right halves respectively
of the indicated word.
If the effective address is less than 1000, the instruction
is an EX JSYS (exec JSYS). Enter monitor mode (leave user mode) and
fetch a double pointer from the real core address (unmapped) equal to
1000 + the effective address. As above, the flags and PC are stored
through the left half pointer and control jumps (in the monitor mode)
to the location indicated by the right half pointer. If this
instruction is executed in EXEC mode, bit 7 of the PC flag word is
affected.
XCT a,E where a is non-zero
XCT a,E in EXEC mode causes the instruction in location E to
be executed with the memory reference(s) relocated by the current
contents of the protection/relocation register or by the map if
mapping is enabled. The different parts of the instruction
referenced are relocated or not depending on the AC field of the XCT.
The AC field bits have the following function:
___________________________________________________
| 10 | 4 | 2 | 1 |
| Efective | Data fetch,| Address | Data store,|
| address |Byte pointer| computation| Byte |
|computation,| fetch, | from |fetch/store,|
|Last address| Pop stack, |byte pointer| Push stack,|
| of BLT |Push memory,| | Pop memory,|
| | 'From' of | | 'To' of |
| | BLT | | BLT |
|____________|____________|____________|____________|
The 10 bit relocates only the memory references of the
efective address calculation. The last address transferred to by a
BLT is relocated when this is on.
The 4 bit causes relocation to be added to any data fetch,
the fetch of a byte pointer, the location of the stack on a POP, the
memory location of the data on a PUSH, and the 'from' address on a
BLT.
When the 2 bit is on, any memory fetches during the address
calculation of the address of a byte are relocated.
The 1 bit causes relocation to be added to any data store,
the fetch or store of a byte, the location of the stack on a PUSH,
the memory location of the data store on a POP, and the 'to' address
on a BLT.
Note that during address calculations, only memory fetches
getting data for the computation are relocated.
FIX AC,233000
The FIX instruction has been added to the PDP-10 and the
PDP-6. FIX on the 10 is op-code 247. The FIX instruction on the 6 is
op-codes 120 through 130 inclusive and 247.
There is a CONS instruction on the PDP-6. If you really
want to know about the CONS instruction, look at the 166 prints.
PDP-10 / PDP-6 DIFFERENCES SECTION 2
MISCELLANEOUS DIFFERENCES
JFFO (op-code 243) is a no-op on the PDP-6.
The PDP-10 has second protect and relocate registers; the
PDP-6 does not.
It is sometimes desirable to pick between seemingly
equivalent instructions on the PDP-6 to get the maximum speed. This
is less often necessary on the PDP-10.
When the READ IN switch is actuated on the PDP-6, the effect
is the same as pushing start, except that the machine will start
executing in shadow memory (real core locations 0-17, not the AC`s).
The PDP-10 however sends a pulse on the I-O buss to a specific
device to load core.
The PDP-6 turns off the byte increment suppression flag when
the PC and flags are being saved at a UUO or PI trap. The PDP-10
turns it off whenever the PC and flags are saved.
The MI cannot be loaded by a program on the PDP-6.
JRST 2,A(XR) may be used to get an indexed return along with
flag restore from the index register. However on the PDP-6 the
flags are restored from the left half of the full-word sum of the
contents of XR and the JRST instruction itself. This is not usually
the desired effect, and indirect addressing should be used instead.
On the PDP-10 this instruction restores the flags from the left side
of XR which is considered the correct operation.
The PDP-10 is equipped with a BBN mapping box and all the
appropriate modifications that go with it have been done. These
include adding the fancy execute mapped features, an inter-processor
interrupt kludge (not connected to another processor), and of course
mapping functions and control. These features are described in the
BBN PAGER instruction manual. There are three new switches in bay 1
of the KA-10: PGR ENB/DIS, JSYS ENB/DIS and MAPAC ENB/DIS. PGR DIS
disables the the pager from seeing the signals EX REL A and MAPAC.
MAPAC DIS disables the pager from seeing MAPAC and therefore causes
the AC base register feature of the pager to be non-existant. JSYS
DIS causes all JSYS to trap to the user.
In the PDP-10, bit 28 of a CONI PTP, is the state of the NXM
STOP key.
In the PDP-10, bit 22 (20000) of CONO PI, causes the APR MEM
PROT flag to be set.
PDP-10 / PDP-6 DIFFERENCES SECTION 2
STATUS REGISTERS
1. PC word
BIT ABBREVIATION PDP-10 FUNCTION PDP-6 FUNCTION
(if different)
0 AROV AR overflow flag
1 CRY0 AR carry 0 flag
2 CRY1 Ar carry 1 flag
3 FOV AR floating overflow PC change flag
flag
4 BIS Byte increment
suppression flag
5 User-mode flag
6 IOT User-mode flag
11 FXU Floating point exponent Not used
underflow flag
12 DCK Divide check flag Not used
2. CONI APR,
BIT PDP-10 FUNCTION PDP-6 FUNCTION
_ (if different)
18 | Not used
19 | PDL overflow flag
20 |_ IOT user mode flag
21 | Address break flag Not used
22 | MEM protect flag
23 |_ Non-ex-mem flag
24 | Not used
25 | Clock interrupt enable
26 |_ Clock flag
27 | Not used
28 | AR FOV interrupt enable PC change interrupt enable
29 |_ AR FOV flag PC change flag
30 | MA TRAP OFFSET Not used
31 | AR OV interrupt enable
32 |_ AR OV flag
33 | \
34 | > Processor PI channel
35 |_ /
PDP-10 / PDP-6 DIFFERENCES SECTION 2
3. CONO APR,
BIT PDP-10 FUNCTION PDP-6 FUNCTION
_ (if different)
18 | Clear PDL overflow flag
19 | I/O bus reset
20 |_ Not used Not used
21 | Clear ADDR break flag Not used
22 | Clear mem protect flag
23 |_ Clear non-ex-mem flag
24 | Clear clock interrupt enable
25 | Set clock interrupt enable
26 |_ Clear clock flag
27 | Clear FOV interrupt enable Clear PC change interrupt enable
28 | Set FOV interrupt enable Set PC change interrupt enable
29 |_ Clear FOV flag Clear PC change flag
30 | Clear AROV interrupt enable
31 | Set AROV interrupt enable
32 |_ Clear AROV flag
33 | \
34 | > Processor PI channel
35 |_ /
4. CONI PI,
BIT PDP-10 FUNCTION PDP-6 FUNCTION
_ (if different)
18 | Power failure flag Not used
19 | Parity error flag
20 |_ Parity error interrupt enable Not used
21 | 1 \
22 | 2 |
23 |_ 3 |
24 | 4 > PI channels in progress Not used
25 | 5 |
26 |_ 6 |
27 | 7 /
28 | PI system on
29 |_ 1 \
30 | 2 |
31 | 3 |
32 |_ 4 > PI channels enabled
33 | 5 |
34 | 6 |
35 |_ 7 /
5. CONO PI,
BIT 22 (20000) ON THE PDP-10 ONLY CAUSES THE APR MEM PROT FLAG TO BE SET.
SUMMARY OF I/O DEVICES SECTION 3
This section lists the I-O devices on the computers at the
project. It supercedes SAILON No. 24, PDP/6 I/O DEVICE NUMBER
SUMMARY by Steve Russell and SAILON No. 25, THE MISCELLANEOUS OUTPUTS
by Steve Russell.
KL10 I/O BUS
Device Number Device
000 PDP-10 APR APR
004 PDP-10 PI system PI
100 PDP-10 paper tape punch PTP
104 PDP-10 paper tape reader PTR
110 167 High speed data channel IOP
120 PDP-10 console teletype TTY
124 Line printer LPT
140 Foonly channel A C1A
144 Foonly channel B C1B
200 136 data control for dectapes and magtapes DC
210 551 dectape control UTC
214 Dectape status UTS
220 516 magnetic tape control MTC
224 Magnetic tape status1 MTS
230 Magnetic tape status2 MTM
300 630 teletype scanner DCSA
304 Teletype scanner DCSB
310 Microswitch Keyboard Scanner DKB
320 DCA Line Scanner DCA
340 Video Switch VDS
344 IOB EXT KL10-PDP6 interface SIX
350 . Thermometer interface HOT
354 . Cart interface CAR
360 . Music KIM interface KIM
364 . Reserved
370 . PA interrupt kluge PK
374 IOB EXT Auto-Dialer DIL
404 Television interface and spacewar buttons TV
430 III Display system control DP
434 III Display system keyboard scanner KBD
444 Librascope disk interface DSK
450 P1/P2 interface P2D
470 10-11 Data interface D11
500 IBM Selector Channel PMP
504 IBM Selector Channel IBM
510 Data Disc controller DDD
530 Mappiplexor MPX
774 Audio Switch AS
KA10 I/O BUS
Device number Device
000 KA10 APR APR
004 KA10 PI system PI
100 KA10 paper tape punch PTP
104 KA10 paper tape reader PTR
120 KA10 console teletype TTY
204 136 data control in Kluge bay DCB
340 IOB EXT P1/P2 interface P1D
344 . Calcomp interface PLT
350 . Varian interface VRN
354 .
360 .
364 .
370 .
374 IOB EXT
410 Sierra Camera driver
420 Electric arms
424 Analog to digital converter AD
440 Xerox Graphics printer XGP
500 Hand-Eye kludge D-to-A's and stepping motor drives
600 Misc. outputs (all channels)
700 Misc. outputs (channels 40 through 77)
730 Electronic clock PCLK
PDP-6 I/O BUS
000 PDP-6 APR APR
004 PDP-6 PI system PI
100 PDP-6 paper tape punch PTP
104 PDP-6 paper tape reader PTR
120 PDP-6 console teletype TTY
240 New A/D converter ADC
244 New D/A converter DAC
340 IOB EXT Dick Moore digital synthesizer FRM
344 . KL10-PDP6 interface INT
350 .
354 .
360 . Music KIM interface KIM
364 .
370 .
374 IOB EXT
540 Samson music box SAMA
544 Samson music box SAMB
550 Samson music box SAMC
554 Samson music box SAMD
SUMMARY OF I/O DEVICES SECTION 3
MISCELLANEOUS OUTPUTS
The DAC's and other miscellaneous functions, such as relay
registers and the hydraulic arm control, are assigned to devices 600
and 700. Within these devices are channels 0 through 77; the
channels 40 through 77 are accessible from both devices, but channels
0 through 37 are available only to device 600.
Both devices accept CONOs and DATAOs. The CONO bits are:
18-29 Data for selected channel
30-35 Channel number
the DATAO word bits are:
12-17 Channel number (low order 6 bits of left half)
18-29 Data for addressed channel (High order bits of right half)
Current channel assignments are:
CHANNEL DEVICE
0 DAC 0
1 DAC 1
2 DAC 2
3 DAC 3
4 DAC 4
5 DAC 5
6 DAC 6
7 DAC 7
10 Hydraulic arm controller
11 Hydraulic arm torque servo
12 Television color wheel
12 Color wheel
15 Hand-eye turntable
16 Turntable solenoid
17 Laser mirror control
40 Television pan, tilt, focus
and Ampex tape recorder remote control
50 Cart DAC 50
51 Cart DAC 51
52 Cart DAC 52
53 Cart DAC 53
54 Cart DAC 54
55 Cart DAC 55
56 Cart DAC 56
57 Cart DAC 57
USING MACHINE INPUT-OUTPUT INSTRUCTIONS SECTION 4
The instructions described below are NOT legal for User mode
programs. (User mode is the normal case.) These instructions can be
executed only in EXEC mode, USER-IOT mode or Spacewar mode. (For
information about USER-IOT mode and Spacewar mode see the UUO
chapter of the monitor manual.)
These instructions cause the CPU that executes them to
transmit and receive data on it's INPUT-OUTPUT BUS. Caution: any
particular device is connected to only one CPU; you must be
executing instructions on the same CPU that the device is connected
to.
OUTPUT INSTRUCTIONS
CONO <DEVICE NUMBER>,E
This instruction transmits the effective address (E) directly
to the device specified by the device number. The effective address
can be indexed and indirected.
DATAO <DEVICE NUMBER>,E
This instruction transmits the contents of the effective
address (E) to the device specified by the device number. The
effective address can be indexed and indirected.
BLKO <DEVICE NUMBER>,E
E: -<WORD COUNT>,,<BUFFER ADDRESS - 1>
This instruction is used to output a large buffer of data to
an I-O device. It uses the effective address (E) to find a pointer
word that contains minus the number of words in the buffer in the
left half and the location of the output buffer minus one in the
right half. BLKO takes the pointer word, increments both halves,
stores it back where it was and then DATAOs (to the specified
device) the contents of the word pointed to by the right half of the
updated pointer word. If the word count in the pointer becomes zero,
the instruction following the BLKO is executed; otherwise it is
skipped. To output a large buffer a loop is created around the BLKO
instruction that continues until the word count reaches zero. After
a buffer is output, the pointer word must be set up again before
doing another BLKO since BLKO clobbers the pointer word.
If BLKO is executed as an interrupt instruction, instead of
skipping if the count is not exhausted, it dismisses the interrupt.
SUMMARY OF I/O DEVICES SECTION 3
USING MACHINE INPUT-OUTPUT INSTRUCTIONS SECTION 4
INPUT INSTRUCTIONS
CONI <DEVICE NUMBER>,E
This instruction transferes the contents of the device's
status register to the effective address.
CONSZ <DEVICE NUMBER>,E
This instruction is used to test whether certain bits of a
device's status register are turned on of not. It fetches the
contents of the device's status register and performes a logical AND
with the the effective address. The next instruction is skipped if
the result zero. If the result is non-zero the next instruction will
be executed.
Logically, CONSZ DEV,E is comparable to:
CONI DEV,AC
TRNE AC,E
except that CONSZ does not clobber an accumulator.
CONSO <DEVICE NUMBER>,E
This instruction is like CONSZ except the next instruction
is skipped if the result of the AND is non-zero, and the
instructions are executed in order if the result is zero.
Logically, CONSZ DEV,E is comparable to:
CONI DEV,AC
TRNN AC,E
except that CONSO does not clobber an accumulator.
DATAI <DEVICE NUMBER>,E
This instruction transfers data from the data register of
the device specified to the effective address.
BLKI <DEVICE NUMBER>,E
E: -<WORD COUNT>,,<BEGINING OF BUFFER MINUS ONE>
This instruction is used to read in a block of data from the
data register of the specified device. It's operation is identical
to the BLKO instruction except that it does input instead of output.
III DISPLAY PROCESSOR SECTION 5
This section supercedes SAILON no. 26 Preliminary
Description of the Display Processor by William Weiher.
The display processor is itself a small computer. The
instructions that it executes form the display. In order for a user
to use the display processor, he must compile display instructions
into his program and ask the system to give these instructions to
the display. See the UUO chapter of the Monitor Manual for details
on user programming.
DISPLAY INSTRUCTIONS
This is a list of the instructions that can be executed by
the display processor. They are executed with no help from the
PDP-10 except that the PDP-10 tells the display processor where to
start.
III DISPLAY PROCESSOR SECTION 5
TSS INSTRUCTION
Test, SET, and Skip
OP-CODE 12
_____________________________________________________________________
|0 7|8 15|16 23|24 30| 31 |32 35|
| RESET | SET | TEST | unused | I | 1010 |
|___________|____________|___________|___________|_______|__________|
A skip condition is generated if any of the eight flags is on
and the corresponding bit in the TEST field is on. If the exclusive
or of the skip condition and bit 31 is true, the next instruction is
skipped. The flags are then set or reset according to the set and
reset field. If both set and reset bits are on, the corresponding
flag is complemented. The flags are as follows:
BITS FLAG
0,8,16 Control bit. This bit may be set, reset, and tested
but has no other meaning to the processor.
1,9,17 Light pen flag. The bit is set if the light pen is
seen.
2,10,18 Edge overflow flag. This bit is set if the beam is
ever positioned off the screen by any means.
3,11,19 Wrap-around flag. This bit is set if overflow occurs
in incremental vector mode.
4,12,20 Not running mask. If this bit is on, the processor
will interrupt if a halt is executed. This bit
cannot be set or reset by this instruction.
5,13,21 Light pen mask. If this bit is on, the processor
will interrupt if the light pen flag comes on.
6,14,22 Edge overflow mask. If this bit is on, the processor
will interrupt if the edge overflow flag comes on.
7,15,23 Wrap-around mask. If this bit is on, the processor
will interrupt if the wrap-around flag comes on.
III DISPLAY PROCESSOR SECTION 5
LVW INSTRUCTION
Long vector word
OP-CODE 06
_____________________________________________________________________
|0 10|11 21|22 24|25 27|28| 29 |30 31|32 35|
| X | Y | BRT | SIZE | | M | T | 0110 |
|___________|___________|_________|_________|__|_____|_____|________|
The long vector word draws one vector with mode, type and
brightness as specified by the M, T, and BRT fields respectively. A 0
in the BRT field indicates no change in brightness. 1 is the dimmest
intensity and 7 the brightest. The brightness affects all vectors
and characters until reset by another long vector word.
Mode 0 indicates relative mode and 1 indicates absolute mode.
In absolute mode, the new position is given by the X and Y components
relative to the center of the screen. In relative mode the
components are added to the current position to give the new
position.
Type;
0-visible
1-end point
2-invisible
3-undefined, currently end point
A visible vector is drawn from the current position to the new
position; the invisible vector moves the beam to the new position
without displaying; the end point vector moves the beam to the new
position and then displays a point.
The size field sets the character size. The selected size is
used for all characters until reset by another long vector word with
a non-zero character size field. The sizes are:
Characters/line Lines/screen
0 no change
1 smallest 128 64
2 85 42
3 73 36
4 64 32
5 42 21
6 32 16
7 largest 21 10
III DISPLAY PROCESSOR SECTION 5
SVW INSTRUCTION
Short vector word
OP-CODE 02
_____________________________________________________________________
|0 6|7 13|14 15|16 22|23 29|30 31|32 35|
| dX1 | dY1 | T1 | dX2 | dY2 | T1 | 0010 |
|_________|_________|________|_________|_________|________|_________|
The short vector word always draws two vectors in relative
mode. The type of each vector is specified by the corresponding T
field. The high order bits of the dX and dY fields are extended left
to give 11-bit quantities.
CHR INSTRUCTION
Character word
OP-CODE 1
_____________________________________________________________________
|0 6|7 13|14 20|21 27|28 34| 35 |
| character | character | character | character | character | |
| 1 | 2 | 3 | 4 | 5 | 1 |
|___________|___________|___________|___________|___________|_______|
The characters are displayed in order from left to right with
automatic spacing. All characters are displayed as printed on the
line printer with the following exceptions:
CODE PRINTS AS
011 ignored
013 integral sign
014 plus or minus
177 circumflex
III DISPLAY PROCESSOR SECTION 5
JMP INSTRUCTION
Jump
OP-CODE 20
_____________________________________________________________________
|0 17|18 30|31 35|
| A | unused | 10000 |
|_________________________________|_____________________|___________|
The processor jumps to location A and continues executing.
HLT INSTRUCTION
Halt
OP-CODE 00
_____________________________________________________________________
|0 17|18 30|31 35|
| unused | unused | 00000 |
|_________________________________|_____________________|___________|
The processor stops with its MA pointing to the location
following the HALT. The not running flag is turned on.
JSR INSTRUCTION
Jump to subroutine
OP-CODE 24
_____________________________________________________________________
|0 17|18 30|31 35|
| A | unused | 10100 |
|_________________________________|_____________________|___________|
This instruction saves a PC word into location A and then
executes code from location A + 1. The PC word is in the same format
as the word stored in location A by the JMS instruction. The word is
also a jump instruction so that the subroutine return can be simply a
jump to A.
III DISPLAY PROCESSOR SECTION 5
JMS INSTRUCTION
Jump to subroutine and save
OP-CODE 04
_____________________________________________________________________
|0 17|18 31|32 35|
| A | unused | 0100 |
|_________________________________|______________________|__________|
The following word of information is written into location A:
_____________________________________________________________________
|0 17|18 22|23 30|31 35|
| MA | CPC | unused | 10000 |
|_________________________________|____________|__________|_________|
CPC: The contents of the CPC buffer register. This register
is loaded whenever the processor discovers an interrupt condition
while processing a character word or short vector word. It is set to
the number of the character being displayed (0-4) or the number of
the vector of the short vector word (0-1). It is reset by a CONO
430, with the clear flags bit on.
The following information is written in location A+1:
_____________________________________________________________________
|0 10|11 21|22 24|25 27|28 35|
| X | Y | BRT | SIZE | FLAGS |
|_____________|_____________|___________|___________|_______________|
The following are the flag bits:
bit 28-control bit
bit 29-light pen flag
bit 30-edge overflow flag
bit 31-wrap around flag
bit 32-wrap around mask
bit 33-light pen mask
bit 34-edge overflow mask
bit 35-always 1
The program then continues executing at A+2.
Note that A is in the form of a jump instruction. This
permits subroutine exit to be done by jumping to A.
III DISPLAY PROCESSOR SECTION 5
SAVE INSTRUCTION
Save
OP-CODE 64
_____________________________________________________________________
|0 17|18 29|30 35|
| A | unused | 110100 |
|_________________________________|_____________________|___________|
The save instruction saves a position word in
location A. This word is in the same format as the word put into A+1
1 by the JMS instruction and is in the correct format to be used by
the Restore instruction.
REST INSTRUCTION
Restore
OP-CODE 14
_____________________________________________________________________
|0 17|18 29| 30 | 31 |32 35|
| B | unused | P | F | 1100 |
|_________________________________|____________|_____|_____|________|
The contents of location B are assumed to be in the format of
the word stored in location A+1 by a JMS or the word stored in
location A by a SAVE. If bit 30 is a 1, the X and Y position
registers and the size and brightness registers are reloaded from the
corresponding fields of this word. If bit 31 is a 1, the flags are
restored.
III DISPLAY PROCESSOR SECTION 5
SEL INSTRUCTION
SELECT (console)
OP-CODE 10
_____________________________________________________________________
|0 11|12 23|24 31|32 35|
| SET | RESET | unused | 1000 |
|____________________|_____________________|_______________|________|
If any of bits 0-11 are 1, the corresponding consoles are
selected. If any of bits 12-23 are 1, the consoles are deselected.
If both the select and de-select bits are on, the state of selection
of that console will be complemented.
III DISPLAY PROCESSOR SECTION 5
PDP-10 CONTROL OF THE DISPLAY PROCESSOR
These instructions are executed by the system to provide
service to all consoles including keyboards and to provide user
created program execution. They are not to be used unless you are
running an exec mode bare machine program.
___________________________________________________________
|18 21|22 25| 26 |27| 28 | 29 | 30 | 31 | 32 |33 35|
CONO 430, | RESET | SET | SC | | NR | F | CONT | STOP | S | PI |
|_______|_____|____|__|____|____|______|______|____|______|
The not running (18,22), edge overflow (19,23), wrap-around
(20,24), and light pen (21,25) mask bits are set and/or reset as
indicated by the bits of the set and reset fields. If both set and
reset bits are on, the mask bits are complemented. If bit 29 is a 1,
the edge overflow, datao interlock, wrap-around, and light pen flags
are cleared. The CPC buffer register is also reset. If bit 32 is 0,
the PI channel is set from bits 33-35.
If the STOP DP bit (31) is 1, the processor will halt at the
end of the current instruction. (The not running flag will turn on.
This will cause an interrupt if the not-running mask is set.) If bit
28 is on, the NOT RUNNING flag will be turned on. This is to cover
up an error where the DP is in fact not running but the flag is not
set.
Any CONO to the DP clears the CLOCK STOP bit. The START
CLOCK bit (26) causes the clock bit to go off for a certain period of
time. After this time, it comes back on again, setting the CLOCK
STOP bit. The CLOCK STOP bit causes the DP to stop after the end of
the current instruction (at which time it will set NOT RUNNING).
If the CONT DP bit is on (30), the processor will begin
executing instructions at the location indicated by its MA.
III DISPLAY PROCESSOR SECTION 5
CONI 430,X
Location X has the following format:
_____________________________________________________________________
|0 11|12 17|18 32|33 35|
| CONSOLES | unused | FLAGS | PI |
|___________________|_____________|__________________________|______|
A 1 bit in the console field (0-11) indicates that the
corresponding console is selected. The flags in bits 18-32 are:
18-Not running; processor is halted
19-Edge overflow flag
20-Wrap around flag
21-Light pen flag
22-Control bit
23-DATAO interlock (PDP-10 gave a DATAO to the processor
while it was running)
24-Interrupt condition (The processor has requested an
interrupt)
25-Non-existent memory
26-Clock
27-DP CHECK COND (The DP wrote in memory below 200000, you
had better fix it!)
28-Clock stop(1)
29-Light pen mask
30-Edge overflow mask
31-Wrap around mask
32-There is a HALT instruction in the FB register
DATAO 430,X
Location X has the following contents:
_____________________________________________________________________
|0 35|
| ANY DISPLAY INSTRUCTION |
|___________________________________________________________________|
The not running flag is turned off, the instruction is
executed, and the processor halts. This will cause DATAO interlock
flag to come on if it is executed when the processor is running. If
it does, the instruction will not be executed.
* III DISPLAY PROCESSOR KEYBOARD SCANNER SECTION 5
Note: The system no longer uses the III keyboard scanner.
__________________________________________________________
|18 28| 29 |30 31| 32 |33 35|
CONO 434, | unused | F | unused | S | PI |
|________________________|_____|____________|_____|______|
If bit 32 is a 1, the PI channel will be loaded from bits 33-35. If
bit 29 is a 1, the scanner flags will be cleared allowing it to
continue scanning.
CONI 434,X
Location X has the following format:
_____________________________________________________________________
|0 3|4 29| 30 |31 32|33 35|
| CONSOLE | unused | I |unused| PI |
|_____________|________________________________|______|______|______|
If bit 30 is a 1, the keyboard is waiting for interrupt
service. "Console" is the number of the console where the scanner has
stopped. The scanner is not released by the execution of the CONI. A
DATAI must be executed before the scanner will continue after a key
has been typed.
DATAI 434,X
_____________________________________________________________________
|0 7| 8 | 9 | 10 |11 13|14 17|18 28|29 35|
|unused| CTRL1 | CTRL2 | SHIFT |unused| CONSOLE | unused | DATA |
|______|_______|_______|_______|______|_________|__________|________|
After the DATAI the scanner will resume scanning.
DATA DISC OPERATION MANUAL SECTION 6
DEVICE SELECT NUMBER: 510
This manual describes the Data Disc Television Display System
and interface (DDTDS&I) at the Stanford A.I. project . The DDTDS&I is
a display system, using a disc with 64 tracks and rotating at 60
r.p.s for data storage. The consoles are standard television
monitors with P31 phosphor to reduce flicker. Each monitor uses one
Channel which is two tracks on the storage disc. The tracks are
switched alternately every 1/60th second--one track for each field of
the standard television raster. Characters are sent to a one-line
buffer and then commanded to be written. They must be written twice;
once for each field.
The DDTDS&I interface is a data channel using the memory-bus
multiplexor in the 2314 interface. To operate it, first the
interface must be CONOed some set up bits, then DATAOed the
(absolute) address of a display program in core. Display
instructions look like this:
Text word.
___________________________________________________________
|0 6|7 13|14 20|21 27|28 35| 35|
| chr1 | chr2 | chr3 | chr4 | chr5 | 1 |
|__________|____________|__________|__________|_________|___|
| | | | | | | | | | | | |
Upon receiving a text word, the interface sends the
characters to the disc's line buffer. Tabs and backspaces are
ignored unless preceded by a backspace (177) in which case, a
special character is printed (i.e. a small tb is printed for tab).
Nulls are always ignored. Carriage return and line feed are
specially processed to do the right thing: If characters have been
transmitted since the last execute command (see command word below),
an execute is generated. Then carriage return causes the interface
to send column select of 2; line feed sends a line address (both
parts) 14 greater than the previous line address sent. Both
carriage return and line feed, if preceded by a 177, print special
characters instead of the above functions.
DATA DISC OPERATION MANUAL SECTION 6
Graphics word
___________________________________________________________
|0 7|8 15|16 23|24 31|32 35|
| byte 1 | byte 2 | byte 3 | byte 4 | 02 |
|____________|_____________|____________|____________|______|
| | | | | | | | | | | | |
The interface sends all 4 8-bit bytes directly to the disc's line
buffer with no modification.
Halt
___________________________________________________________
|0 29|30 35|
| unused | X0 |
|_________________________________________________|_________|
| | | | | | | | | | | | |
A halt is executed on op-codes 0,40, and 60. A halt word does just
that, and sets the halt bit which can be read by a CONI. The bit is
reset by a CONO. If the halt interrupt enable bit is on, the device
interrupts.
Jump
___________________________________________________________
|0 17|18 29|30 35|
| jump address | | 20 |
|_____________________________|___________________|_________|
| | | | | | | | | | | | |
A jump word causes the MA to be loaded with the Contents of the left
half of the word and execution continues from there.
NO OPERATION
___________________________________________________________
|0 17|18 29|30 35|
| unused | unused | XX |
|_____________________________|___________________|_________|
| | | | | | | | | | | | |
Op-codes 06,10,12, and 16 have no function. The controller skips
over them and proceeds. Do not use no-ops frequently especially
during text output as each one takes about two microseconds.
DATA DISC OPERATION MANUAL SECTION 6
Command word
___________________________________________________________
|0 7|8 15|16 23|2426|2729|3032|3335|
| data 1 | data 2 | data 3 |op 1|op 2|op 3| 4 |
|____________|____________|_____________|____|____|____|____|
| | | | | | | | | | | | |
A command word causes the interface to send DD three command bytes
with the op-codes specified. The commands possible are as follows:
OP-CODE USE
0 Execute: Empties line buffer onto the disc at
the position previously specified.
Data is irrelevant.
1 function code: Loads function code register. Bits
will be explained later.
2 channel select: Channel specified in data is selected
for writing. If erase bit is on and
graphics mode bit is set, the channel
selected is erased to the background
selected by the dark/light bit.
3 column select: Data is loaded into the column
register and the line buffer address
register. This sets the X position
of your output. Column 0 is illegal
and will hang the controller. Column
85 is the last column to be displayed
with characters; characters sent for
columns 86-128 are flushed, over 128,
you wrap around. A column select
greater than 85 will also hang the
controller. The last graphics column
is 64 and columns greater than that
will hang the controller.
4 high order Data is loaded into the high order
line address: 5 bits of the line address.
5 low order Data is loaded into the low order 4
line address: bits of the line address. Line range
is from 0 to 737 (octal). Line
addresses between 740 and 777 cause
execute commands to be ignored.
Above 777 wraps around.
6 write directly: Data is written directly on the disc
at the location previously set up
without using the line buffer. The
column address is automatically
incremented. Executes are not
necessary.
7 line buffer Data is loaded into the line buffer
address: address only. This allows some of
of the line buffer contents to be
changed and the rest retained. The
first character displayed will be the
one specified by the column address,
and the last character will be the
last one sent after this command.
The function code register has the following format:
8 7 6 5 4 3 2 1
_______________________________________________________________
| | |single |nospace|2 wide | dark | write |graphic|
|unused |unused |height | (add) |(erase)| back |enable | mode | 1
|_______|_______|_______|_______|_______|_______|_______|_______|
| | |double | space | | light |display| alpha |
|unused |unused |height | (rep) |1 wide | back |direct |numeric| 0
|_______|_______|_______|_______|_______|_______|_______|_______|
MSB | | LSB |
single height/double height: Single height characters are
40 12 lines tall; 10 lines above the "base" line and 2 lines
bit below. Top line of character prints on the line addressed.
This bit has no effect in graphics mode.
space/nospace: when this bit is on, characters are
20 substituted on top of the line previously written; when off,
bit remainder of line is erased. In graphics mode this bit does
this:
additive/replacement: When this bit is on, only 1 bits are
20 written, ORed with the bits already written; when off, 1's and
bit 0's are written clobbering previous data. CAUTION!: when
(G) replacing, the bits at the beginning and end of the line
segment you are writing should be the same as the previous
data or bit lossage may occur.
double width/single width: With this bit on, characters
10 are 5 bits wide with a 0 bit on the end (total 6 bits);
bit characters are 10 bits wide with two 0 bits on the end when
the bit is off. CAUTION!: When using double width characters,
do not exceed 43 characters in a line or the controller will
hang. In graphics mode this bit does this:
10 erase: in graphics mode, if this bit is on, the screen will
bit be erased to the background selected when a channel select is
(G) done.
dark/light: When this bit is on, erase causes screen to
4 go dark and characters and graphic 1 bits are light. When off,
bit erase goes to light and characters and graphic 1 bits are
dark.
write/display directly: When this bit is on, operations go to
2 the disc. When off, data is displayed once on the selected
bit channel and then goes away and previous data remains.
1 alphanumerics/graphics: When this bit is on, you are in
bit graphics mode; you are in alphanumeric mode when it is off.
DATA DISC OPERATION MANUAL SECTION 6
IOT's to Data Disc Interface
CONI 510,
_____________________________________________________________________
|18 24| 25 | 26 | 27 | 28 | 29 | 30 |31 | 32 |33 35|
| | non|user|late| |halt| | | | |
| unused | ex | |int |late|int |field|int|halt| PI |
| | mem|mode|enb | |enb | | | | |
|________________|____|____|____|____|____|_____|___|____|__________|
| | | | | | |
PI field is the PI channel currently in the PI register.
Halt bit means the interface has finished its current buffer and has
not been re-initialized.
Int bit means the interface is now interrupting on the channel loaded
into it's PI register.
Field bit is 0 during the even field rotation of the disc, and a 1
during the odd field.
Halt int enb bit means the interface is enabled to interrupt when it
halts.
Late bit is set if, during a write directly transfer, the interface
falls behind the disc. When this happens that line should be
retransmitted.
Late int enb bit means the interface is enabled to interrupt when the
late flag comes on.
User mode bit allows the first channel select (from a command word)
to have its proper effect. All other channel selects are ignored
until the next CONO.
Non ex mem bit means that the interface tried to access non existant
memory.
CONO 510,
____________________________________________________________
|18 25| 26 | 27 | 28 | 29 | 30 | 31 |32 |33 35|
| |user|late| | |halt|force|re-| |
| unused | |int |SPGO|DDGO|int | |set| PI |
| |mode|enb | | |enb |field| | |
|___________________|____|____|____|____|____|_____|___|__________|
| | | | | | |
PI field sets PI register to channel indicated.
Reset bit causes Data Disc to be reset. This should be done if the
controller is hung up for some reason like a column number is too
large.
Force field bit, when set, causes Data Disc to look at the low order
bit of the line address. This indicates which field the characters
go out on. Both fields must be written for complete characters.
When this bit is off, the characters are written on the first field
that comes around. This bit has no effect on graphics data.
Halt int enb bit sets or resets the halt interrupt enable which
enables interrupts when the interface halts.
DDGO sets or resets the DDGO flip-flop in the interface. This must
be set if you want the interface to talk to Data Disc.
SPGO bit sets or resets the SPGO flip-flop in the interface. This
should never be set. It is to be used for some device in the sky
that could go through the same interface.
Late int enb sets or resets the late interrupt enable which enables
interrupts when the late bit comes on.
User mode bit allows the first channel select (from a command word)
to have its proper effect. All other channel selects are ignored
until the next CONO.
DATAO 510,
___________________________________________________________
|0 17|18 35|
| unused | starting address |
|_____________________________|_____________________________|
| | | | | | | | | | | | |
A DATAO to the interface loads the memory address register with the
right half of the data and starts the interface at that location.
VIDEO SWITCH SECTION 7
The video switch is a logic matrix connecting the 32 Data
Disk display channels and up to 7 analog video sources to up to 64
video monitors (normally consoles). Each monitor may independently
be switched to any combination of Data Disk channels, and also to
any one of the 7 analog video sources, or none. Selecting multiple
sources produces an output which is the MAX (i.e. most "white") of
the selected inputs. This means that Data Disk "white-on-black"
channels can be properly superimposed, but "black-on-white" channels
cannot. Data Disk sync signal is normally supplied along with the
video, but this can be suppressed when necessary to view an analog
source which is not synchronous with Data Disk video. Naturally,
combining such a signal with any Data Disk output will not produce
the desired effect.
Control of the video switch is fairly simple. Associated
with each of the 64 output channels is a 36-bit register which
determines which sources are selected to that output. Loading a
given register is accomplished by doing a CONO to select the channel
and a DATAO of the desired map data. More detail is given below.
CONO 340,:
18-29 Unused
30-35 Channel to be affected by subsequent DATAOs
DATAO 340,:
0-31 DD channel selection mask.
A 1 in bit position N enables DD channel
N in the output; a 0 disables it.
32 DD sync inhibit (for use with nonsynchronous analog sources)
33-35 Analog channel selection, 1-7; 0=> none.
ANALOG CHANNEL ASSIGNMENTS:
1 Cohu TV camera (hand-eye table)
2 Sierra TV camera (hand-eye table)
3 Kintel TV camera (movable)
4 Cart receiver
5 Lounge TV set
6 Secondary video synthesizer (or chroma of color synthesizer)
7 Primary video synthesizer
* KEYBOARD SCANNER OPERATION MANUAL SECTION 8
DEVICE 310
The keyboard scanner is a TTL device scanning 64 keyboards
(or other devices with no more than 12 bits output). Devices scanned
must put out TTL compatible signals and have a strobe to signal data
ready. The scanner polls each device's flag in turn. When it finds
a flag that is set, it stops scanning and interrupts the computer.
The scanner also has a mode (SPW mode) which enables the computer to
send a line address and then read the data from that line without a
flag being present. The flag is set by a positive transition of the
strobe line, and the strobe is read into the computer along with the
12 bits from the device. This enables the computer to know if it has
missed the data (i.e. the keyboard's strobe goes away if two keys are
pressed at once, or if the user gets his finger off the key before
the computer can service his interrupt). If you are sneaky and have
a device that reads out 13 bits, the strobe line can be used as a bit
if the scanner is used in SPW mode.
To operate the scanner, first a CONO is sent to set up the PI
channel and to clear the scanner if necessary. Then when an interrupt
occurs from the scanner, a DATAI gets you the line number and the
data. After the DATAI is completed, the scanner clears the flag of
the line it just read, and resumes scanning. To operate in SPW mode,
a DATAO is sent with the line number and the SPW bit on, then a DATAI
gets you the data and the line number to make sure you got the right
thing. This shuts off SPW mode and returns the scanner to normal
operation. When in SPW mode, the scanner still scans, and if it
finds a set flag, it waits. When the SPW DATAI is done, the scanner
interrupts immediately. No interrupts occur in SPW mode.
* KEYBOARD SCANNER OPERATION MANUAL SECTION 8
The IOT's have the following format:
CONO 310,
_______________________________________________________________
|18 31| 32 |33 35|
| unused |CLEAR| PI |
|_________________________________________________|_____|_______|
The PI channel is set to the number in the PI field, and the
clear bit clears all flags, SPW bit, and the interrupt bit.
CONI 310,
______________________________________________________________
|18 30| 31| 32|33 35|
| unused |SPW|INT| PI |
|______________________________________________|___|___|_______|
The SPW bit says that the scanner is in SPW mode; the INT bit
says the scanner is requesting an interrupt; the PI field shows which
channel the scanner is currently set up to interrupt on.
DATAI 310,
___________________________________________________________
|0 11|12 17|18 21| 22| 23|24 35|
| unused |LINE NUMB|unused|SPW|STR| msb DATA lsb |
|___________________|_________|______|___|___|______________|
| | | | | | | | | | | | |
The line number is where this data came from, SPW means you
were in SPW mode, STR is the strobe bit, DATA is the 12 bit data.
DATAO 310,
___________________________________________________________
|0 17|18 22|23 |24 29|30 35|
| unused |unused|SPW| unused |LINE NUMB|
|_____________________________|______|___|________|_________|
| | | | | | | | | | | | |
The line to be read in SPW mode is set from the line numb
field, and the SPW bit is to make sure you really mean it. This will
hang the scanner until a DATAI is done so use it carefully.
167 HIGH SPEED CHANNEL SECTION 9
The 167 is used to read data in and out of memory to the
Librascope disk, and to read data into core from the television
camera analog to digital converter. The 167 is not to be accessed by
users; this section is for system programmers only. IOP is 110.
CONO 110,
CONI 110,
These instructions transfer the following data to/from the
processor from/to the 167.
BIT _ ___ FUNCTION
18 |___ unused
19 |___ Early response
20 _|___ Parity error
21 |
22 | unused
23 _|
24 |
25 |
26 _|___
27 |___ Init
28 |___ Ready
29 _|___ I/O (0=in, 1=out)
30 |___ Data Missed
31 |___ Non-ex Mem
32 _|___ Job Done
33 |
34 | PI Channel
35 _|___
DATAO 110,
DATAI 110,
These instructions transfer the word count and the memory
address to/from the 167 from/to the processor. The word count is in
the left half of the word and the memory address is in the right.
* LIBRASCOPE DISK FILE SECTION 10
The Librascope disk is not to be accessed directly by users;
the system provides UUOs for using it which are described in the UUO
chapter of the Monitor Manual.
CONO 444,
This instruction sets up the PI interface.
BIT _ ___ FUNCTION
18 |
19 |
20 _| unused
21 |
22 |___
23 _|___ reset CND DER INT
24 |___ reset CND TI
25 |
26 _|
27 |
28 | unused
29 _|
30 |
31 |
32 _|___
33 |
34 | PI Channel
35 _|___
DATAO 444,
This instruction sets up the Disk Address. It can be
executed twice, once with bit 0 on and once with bit 0 off.
BIT _ ___ FUNCTION
0 |___ If 0, use ↓this list↓ If 1, use ↓this list↓
1 |
2 _|
3 |
4 |
5 _|
6 |
7 |
8 _| unused
9 |
10 |
11 _|
12 |
13 | unused
14 _|
15 |___
16 | Band 0
17 _| Band 1
18 | Band 2
19 | Band 3
20 _| Band 4
21 | Band 5
22 | Band 6
23 _|___ Band 7
24 |___ Track Set
25 | Sector Address 0 Sector Counter Register 0
26 _| Sector Address 1 Sector Counter Register 1
27 | Sector Address 2 Sector Counter Register 2
28 | Sector Address 3 Sector Counter Register 3
29 _| Sector Address 4 Sector Counter Register 4
30 | Sector Address 5 Sector Counter Register 5
31 | Sector Address 6 Sector Counter Register 6
32 _| Sector Address 7 Sector Counter Register 7
33 | Sector Address 8 Sector Counter Register 8
34 | Sector Address 9 Sector Counter Register 9
35 _|___ Sector Address 10 Sector Counter Register 10
;A band stores 76*1024 words in two revolutions of the disk. Each
;band is logically two tracks, each track containing =1216 32-word
;sectors. The sector address register counts from 0 to =1215 and then
;complements TRACK SET, and resets the sector address to 0. The
;librascope can start anywhere in a band (2 revolutions) and read or
;write the entire band in one operation. Legal band numbers are from
;0 to =143, but the only bands that still work are within the range
;=48 to =119 (and not all bands in that range work).
A band stores 76*1024 words, 38*1024 in each of two track sets, each
containing =1216 32-word sectors. The sector address regiater counts
from 0 to =1216 and resets to 0. The Librascope can start at the
beginning of any sector and read or write the entire track set of that
band in one operation; if the word count is big enough, the sector
counter will wrap aound to the beginning of the track set and continue.
Legal band numbers are from 0 to =143, but the only bands that still
work are within the range =48 to =119 and not all the bands in that
range work in either or both track sets.
DATAI 444,
This instruction reads the sector counter.
BIT _ ___ FUNCTION
18 |
19 |
20 _|
21 | unused
22 |
23 _|___
24 |___ SCI
25 | Sector Counter 0
26 _| Sector Counter 1
27 | Sector Counter 2
28 | Sector Counter 3
29 _| Sector Counter 4
30 | Sector Counter 5
31 | Sector Counter 6
32 _| Sector Counter 7
33 | Sector Counter 8
34 | Sector Counter 9
35 _|___ Sector Counter 10
CONI 444,
This instruction gives the status of the disk.
BIT _ ___ FUNCTION
18 |
19 |
20 _|
21 | unused
22 |
23 _|
24 |___
25 |___ CND DER INT
26 _|___ CND TI
27 |___ Off line
28 |___ Hot
29 _|___ Slow down
30 |___ Sector address error
31 |___ Write error
32 _|___ Read error
33 |
34 | PI channel
35 _|___
A short example of bare machine use of librascope:
START: CONO DSK,14000 ;clear error indicators
CONO IOP,0 ;or CONO IOP,100 for output
DATAO IOP,[-WC,,MA] ;WCMA for the channel
JFCL ;wait for channel to get ready
JFCL
JFCL
DATA DSK,[BAND*10000+SECTOR] ;send the disk its address
....
WAIT: CONSZ IOP,10 ;done?
JRST DONE ;yes
CONSO DSK,3770 ;Librascope error?
CONSZ IOP,300060 ;or IOP error?
JRST ERROR ;some error
JRST WAIT ;loop waiting for something.
TELEVISION CAMERA INTERFACE SECTION 11
The television camera is handled for the user through
special UUOs described in the UUO chapter of the Monitor Manual.
However, if you intend to use the camera you should read this
section because the bit format is the same as in the UUOs.
CONO 404,
This instruction sets up various parameters for the picture
in the following format.
BIT _ ___ FUNCTION
18 |
19 | BCLIP
20 _|___
21 |
22 | TCLIP
23 _|___
24 |
25 | Camera Number
26 _|___
27 |
28 | Vertical Resolution (normally 0)
29 _|___
30 | 0
31 | 0
32 _| 0
33 | 0
34 |___ 1
35 _|___ Offset left 1/2 sample
DATAO 404,
This instruction sets up the size of the picture and starts
the transfer.
BIT _ ___ FUNCTION
0 |
1 |
2 _|
3 | First line
4 |
5 _|
6 |
7 |
8 _|___
9 |
10 |
11 _|
12 | Horizontal offset
13 | (in samples)
14 _|
15 |
16 |
17 _|___
18 |
19 |
20 _|
21 | Width (in words)
22 |
23 _|
24 |___
25 |
26 _|
27 |
28 |
29 _|
30 | unused
31 |
32 _|
33 |
34 |
35 _|___
DATAI 404,
This instruction reads the line counter.
BIT _ ___ FUNCTION
18 |
19 |
20 _|
21 |
22 | unused
23 _|
24 |
25 |
26 _|___
27 |
28 | Line counter 1
29 _| Line counter 2
30 | Line counter 3
31 | Line counter 4
32 _| Line counter 5
33 | Line counter 6
34 | Line counter 7
35 _|___ Line counter 8
CONI 404,
This instruction is unused by the television interface so it
is utilized to read the spacewar buttons by the Hand-Eye table.
* TELEVISION PAN, TILT, AND FOCUS SECTION 11.1
*** As of 1-Jan-1980, this piece of eqiupment has been put out to pasture. ***
*** ROB ***
The television is equipped with a remotely operated pan-tilt
head and has remotely controlled focus and lens turret. These
functions can be controlled by the computer when the switch on the
black control box "COM-MAN" is in the "COM" position. To operate
these functions manually, the switch must be in the "MAN" position.
To control the camera, you must execute:
CONO 600,<SELECT WORD>.
The select word has the following format:
BIT NO._ ___ FUNCTION
18 |___ tilt back
19 |___ tilt forward
20 _|___ pan left
21 |___ pan right
22 |___ focus far
23 _|___ focus near
24 |___ actuate turret
25 |
26 _|
27 |
28 |
29 _|___
30 | 1
31 | 0 CHANNEL
32 _| 0
33 | 0
34 | 0 SELECT
35 _|___ 0
In order to operate any of the above functions, the CONO
must be sent with the bit or bits on for the operation required to
start the movement. Then a CONO 600,40 must be sent when the
movement is required to be stopped. To actuate the turret, the bit
should be left on for less time than it takes to rotate the turret
to the position desired, but for at least 15 tics. Experiment will
quickly show how long it should be left on for proper operation.
The position of the pan-tilt head and of the focus mount can
be read by the computer using the analog to digital converter. The
focus mount is connected to A/D channel 17, the tilt to 20, and the
pan to 21. See section II.E.6 THE AD-DA CONVERTER of chapter II of
the monitor manual (SAILON No. 55) for operation of the A/D.
* TELEVISION COLOR WHEEL AND TURRET POSITION SECTION 11.2
The television is equipped with a four position color
wheel that can be rotated under computer control. The computer
can also read the position of the color wheel as well as the
position of the lens turret. The color wheel can be rotated
by sending a CONO 600,<SELECT WORD>. The select word has the
following format:
BIT NO._ ___ FUNCTION
18 |
19 |___ color
20 _|
21 |
22 |
23 _|
24 |
25 |
26 _|
27 |
28 |
29 _|___
30 | 0
31 | 0 CHANNEL
32 _| 1
33 | 0
34 | 1 SELECT
35 _|___ 0
The filters now in the color wheel are addressed in the
following way:
BIT 18 19 COLOR
0 0 red
0 1 blue
1 0 green
1 1 clear
The color now in position can be read along with the position
of the turret and a bit that says the color wheel is not moving.
The colors are the same as in the above chart and the turret position
is arbitrary, as the lenses may be installed in any position. This
information can be gotten by executing a CONI 600,E and E will have
the following format:
BIT NO._ ___ FUNCTION
18 | color wheel
19 |___ position
20 _|___ wheel not moving
21 | turret
22 |___ position
23 _|
24 |
25 |
26 _|
27 | unused
28 |
29 _|
30 |
31 |
32 _|
33 |
34 |
35 _|___
* HAND-EYE TABLE TURNTABLE SECTION 11.3
The hand-eye table has a turntable in the surface to make
stereo vision possible with only one camera by moving the world. the
turntable has a stepping motor to drive it so that one step of the
motor equals one minute of arc movement of the turntable. To move
the turntable, you execute a CONO 600, <SELECT WORD>. The select
word has the following format:
BIT NO._ ___ FUNCTION
18 |___ direction
19 | speed
20 _|___
21 |___ GO
22 |
23 _|
24 |
25 |
26 _|
27 |
28 |
29 _|___
30 | 0
31 | 0 CHANNEL
32 _| 1
33 | 1
34 | 0 SELECT
35 _|___ 1
When the direction bit is 0, the turntable moves clockwise, and
anti-clockwise when the bit is 1. The speed field controls how many
steps are moved every time the CONO is executed. The speeds are as
follows:
BIT 17 16 STEPS PER EXECUTION
0 0 1
0 1 2
1 0 4
1 1 8
The highest speed is unreliable in that stopping and starting it may
miss or invent steps. It can be used by starting up at a low speed
and then switching high speed, then to stop, slow down first and then
stop. You also have to check if you are about to be shuffled, and
slow down. All CONOs must have the GO bit on to have an effect.
The turntable motor can be disengaged to allow the turntable to
freewheel by sending a CONO 600,16. A CONO 600,15 engages it again.
The motor must be engaged before trying to move the turntable.
* LASER MIRROR CONTROL SECTION 11.4
*** NOTE: This device has been flushed as of 1-May-79, and is ***
*** included here for hyterical reasons. ***
A stepping motor is provided on the hand eye table with a
mirror mounted on it. It can be advanced one step at a time in
either direction. The shaft is stepped every time a CONO 600,<SELECT
WORD> is executed. The select word has the following format:
BIT NO._ ___ FUNCTION
18 |___ direction
19 |
20 _|
21 |
22 |
23 _|
24 | unused
25 |
26 _|
27 |
28 |
29 _|___
30 | 0
31 | 0 CHANNEL
32 _| 1
33 | 1
34 | 1 SELECT
35 _|___ 1
The direction bit is 0 for clockwise, and 1 for anti-clockwise.
* STANFORD ELECTRIC ARM SECTION 13
The Stanford electric arm is a manipulator with six degrees
of freedom and a parallel jaw hand. It was designed by Victor
Scheinman; a full description is contained in his Ph.D. thesis for
the Mechanical Engineering Department.
Each joint of the arm and hand has a potentiometer that can
be read with the analog to digital converter to determine the
position of the arm at any moment. The pots for the Stanford arm are
connected to A/D channels 55 through 63 in the order you would
expect. See the UUO chapter of the Monitor Manual for user
operation of the A/D.
To move an arm, first the speed should be set up. The speed
is controlled by digital to analog converters 0 through 6, assigned
in the same order as above. See the A/D and D/A writeup in this
manual and the UUO manual for operation of the DACs. A DAC value of
200 awill give practically no movement at all while a value of 177
will give maximum speed which is too fast in most cases.
Experimentation and advice will tell you what speeds are best for
each joint.
* STANFORD ELECTRIC ARM SECTION 13
In order to actuate an arm, it is necessary to execute a
DATAO 420,[SELECT WORD]. The select word contains the magic bits
telling each joint what to do and which arm to do it to. The
following is the selection word format:
BIT NO._ ___ FUNCTION
0 |___ joint 1
1 |___ joint 2 STANFORD
2 _|___ joint 3 ELECTRIC
3 |___ joint 4 ARM
4 |___ joint 5 BRAKES
5 _|___ hand
7 |
. |
. | unused
. |
17 _|___
18 |___ joint 1 direction
19 |___ joint 1 GO
20 _|___ joint 2 direction
21 |___ joint 2 GO
22 |___ joint 3 direction
23 _|___ joint 3 GO
23 |___ joint 4 direction
25 |___ joint 4 GO
26 _|___ joint 5 direction
27 |___ joint 5 GO
28 |___ joint 6 direction
29 _|___ joint 6 GO
30 |___ hand direction
31 |___ hand GO
32 _|___ unused
33 |___ Rancho arm (no longer in use)
34 |___ Stanford arm
35 _|___ un-kill Stanford arm
When a DATAO is sent with a GO bit on, that joint`s motor
will be sent a pulse proportional in length to the output signal of
the DAC. The direction bit controls the direction of the joint.
Which direction each joint goes for direction bit on or off is hard
to describe, so experimentation is probably the best method for
determining that. The usual mode for operating the arm is to send
the DATAO every spacewar tic, changing the values of the DACs for
speed control and the direction bits in the selection word for
direction control. The GO bits should be turned off when no motion is
desired because even when the speed is set to 200 the joint may tend
to drift. Bits 33 and 34 tell the arm controller which arm this
command is for.
The Stanford arm has brakes on all joints but 6, and they are
actuated by bits 0 through 5 in the DATAO. The brakes are applied
when the bit is 0, and released when the bit is 1. There is a box on
a cable that plugs into the controller that has 6 white switches and
a red pushbutton. Each switch controls the brakes for one joint.
When the switch is on, the corresponding brake is released,
otherwise, the brake is under computer control. When the red button
is pushed, the Stanford arm stops, and turns on all of its brakes.
This condition persists until a DATAO is executed with the "un-kill"
bit on. When the un-kill bit is on, no GO bits should be on. If a
DATAO to the Stanford arm is not sent every 16 milliseconds, the arm
stops and applies its brakes until the program resumes.
* THE ANALOG TO DIGITAL CONVERTER AND MULTIPLEXER SECTION 14
* THE DIGITAL TO ANALOG CONVERTER SECTION 15
The digital to analog converter is connected to channels 0
through 7 of device 600 on the PDP-6 I-O buss. There are actually 8
separate converters, each of which is accessed individually. In
order to set up the converter you must execute a CONO 600,<DATA &
SELECT>. The data and select bits have the following format:
BIT _ ___ FUNCTION
18 |
19 |
20 _| unused
21 |___
22 |
23 _|
24 |
25 | data
26 _| bits
27 |
28 |
29 _|___
30 |
31 | all zeroes
32 _|___
33 |
34 | DAC number
35 _|___
Bits 30 to 35 select which channel of device 600 is to be accessed.
DACs 0 through 7 are on channels 0 through 7, so bits 30 to 32 should
all be zeros and bits 33 to 35 are the DAC number. The data to the
digital to analog converter is in signed twos complement. This means
that for 0 data, the output is -5 volts, for data of 200, the output
is 0 volts, and for a value of 177, the output is approximately -10
volts. The logical progression for 0 to 10 volts is as follows:
VALUE VOLTAGE(negative)
200 0.0
201 0.0390625
202 0.078125
204 0.15625
210 0.3125
220 0.625
240 1.25
300 2.5
000 5.
100 7.5
140 8.75
160 9.375
170 9.6875
174 9.84375
176 9.921875
177 9.9609375
Thus if a voltage of 3.06875 volts is desired to come out of DAC 5,
execute a CONO 600,31405.
* ELECTRONIC CLOCK SECTION 16
The electronic clock is attached to the PDP-6 I-O Bus and
gives the time in microseconds, seconds, minutes, hours, days,
months, and year. SAILON 9, ELECTRONIC CLOCK by Phil Petit gives a
detailed description of the clock and its electronics. This section
is meant as a quick reference only; if any problems arise, check in
that SAILON.
To read the clock, a DATAI 730,E must be executed on the
PDP-6. Location E will contain a word interpreted as follows:
BIT _ ___ DATA
0 |___ clock invalid
1 |___ year invalid
2 _|
3 |
4 |
5 _| unused
6 |
7 |___
8 _|
9 | year first digit
10 |
11 _|___
12 |
13 |
14 _| year second digit
15 |___
16 |
17 _|
18 | month
19 |___
20 _|
21 |
22 | day
23 _|
24 |___
25 |
26 _|
27 | hour
28 |
29 _|___
30 |
31 |
32 _|
33 | minute
34 |
35 _|___
* ELECTRONIC CLOCK SECTION 16
First check to see that the two invalid bits, bits 0 and 1,
are both 0. If bit 0 is on, start over. If bit 1 is on, the clock
needs to be set, so get someone who knows how to do it. Now subtract
601004 from E and the data will be in a form you can use:
bits 8 to 11 contain the tens digit of the year (0 to 11)
bits 12 to 15 contain the ones digit of the year (0 to 11)
bits 16 to 19 contain the month (1 to 14)
bits 20 to 24 contain the day (1 to 37)
bits 25 to 29 contain the hour (0 to 30)
bits 30 to 35 contain the minute (0 to 73)
bit numbers are decimal, data is octal.
Now read the fast part of the clock by executing a CONI
730,E. Interpret the data that appears in location E as follows:
BIT _ ___ DATA
0 |
1 |
2 _| unused
3 |
4 |
5 _|___
6 |
7 | minutes
8 _|
9 |___
10 |
11 _|
12 | seconds
13 |
14 _|
15 |___
16 |
17 __|
18 | milliseconds
THRU |
35 _|___
Now subtract 2020136700 from E and data will be as follows:
bits 6 to 9 contain the 4 low order bits of the minute counter
bits 10 to 15 contain the seconds (0 to 73)
bits 16 to 35 contain the millisecond (0 to 3641077)
bit numbers in decimal, data in octal.
It is nice to check that the CONI and the DATAI were not
separated by a change in the minute. Check that bits 6 to 9 of the
CONI word are the same as bits 32 to 35 of the DATAI word. If you
are doing something like program timing, it is only necessary to
execute the CONI.
XEROX GRAPHICS PRINTER SECTION 17
The Xerox Graphics Printer (XGP) makes hard copy from raster
bit matrices. The paper is 8.5 inches wide and any length. The
line is approximately 1700 bits wide. There are approximately 200
lines per inch along the paper.
The XGP has a paper cutter that can be used in two modes.
The "CUT NOW" command cuts the end of the paper off. This is 22
inches from the line you are printing now. The "MARK & CUT" command
puts a mark on the paper at the present printing line and when it
gets to the cutter, it (that is, the paper) is terminated with
extreme prejudice.
The interface has two buffers, each 2K X 1 bits. One buffer
can be loaded while the other is feeding bits out to the XGP. Then
the buffers are swapped and the process repeats. The interface can
be enabled to set "DONE", which comes up at the end of a line and
interrupts. At this point, you swap the buffers, and begin to load
the other buffer.
XEROX GRAPHICS PRINTER SECTION 17
CONI 440,
18 ----
|
| UNUSED
|
----
|
28 | PAPRLO
29 | XGPOK
----
30 | VIDENB
31 | NZ
32 | DONE
----
33 |
34 | UNUSED (MAY BECOME PI CHANNEL)
35 |
----
The PAPRLO bit means that the XGP is almost out of paper. Don't
expect any long listings to finish.
When the XGPOK bit is on, this means that the XGP is ready to
receive data.
VIDENB is true during the scan line and off during retrace.
When NZ is set, the interface is ready to accept another byte
of data.
Done is set when the XGP reaches the end of it's scan line.
It is reset by a CONO.
XEROX GRAPHICS PRINTER SECTION 17
CONO 440,
----
18 | X
19 | X
20 | 1
----
21 | 1
22 | 0
23 | 0
----
24 |
|
| BIT ADDRESS
|
35 |
----
This command loads the address register of the buffer
currently being loaded. All commands that load the buffer register
will start loading at this address and leave the register pointing
one location beyond the last bit loaded.
The address register must be zeroed before swapping buffers
so that the XGP unloads the buffer from the beginning.
XEROX GRAPHICS PRINTER SECTION 17
CONO 440,
----
18 | X
19 | X
20 | 1
----
21 | 1
22 | 0
23 | 1
----
24 |
|
| N
|
35 |
----
This command starts at current address of current buffer and
loads N one bits. This will take about N*120 ns. Check "NZ" before
sending any more commands!
Note that if N<35 you needn't check NZ because the CONO takes
longer than that.
XEROX GRAPHICS PRINTER SECTION 17
CONO 440,
----
18 | X
19 | X
20 | 1
----
21 | 1
22 | 1
23 | 0
----
24 |
| UNUSED
26 |
----
27 | UNUSED
28 | UNUSED
29 | DONE ENABLE
----
30 | BLANK
31 | XGPON
32 | CLEAR DONE
----
33 |
34 | PI CHANNEL
35 |
----
"DONE ENABLE" enables the setting of "DONE" at the end of the
scan line. "DONE" interrupts.
Setting "BLANK" causes the data in the buffers to be ignored,
and blank paper to be emitted.
"XGPON" starts the paper moving. When it is turned off, the
printer will spew 22 inches of paper and then stop.
"CLEAR DONE" clears "DONE". DONE must be cleared or you never
get another interrupt.
XEROX GRAPHICS PRINTER SECTION 17
CONO 440,
----
18 | X
19 | X
20 | 1
----
21 | 1
22 | 1
23 | 1
----
24 |
25 | UNUSED
26 |
----
27 |
28 | UNUSED
29 |
----
30 |
31 | UNUSED
32 |
----
33 | SWITCH LINE BUFFERS
34 | CUT NOW
| MARK & CUT
----
Note: remember to zero the bit address before switching
buffers. The CUT NOW command cuts the paper right now, 22 inches
away from where you happen to be printing. The MARK & CUT command
will cut the paper at the place you're writing now. Caution: Leave
blankness near a MARK because the hardware isn't too careful about
exactly where it cuts.
XEROX GRAPHICS PRINTER SECTION 17
DATAO 440,
----
18 | X
19 | 0
20 | VIDEO
---- ↑
21 | |
| |
| |
| |
| |
| ↓
35 | VIDEO
----
This instruction loads 16 bits of video data into the current
buffer. It loads from the current address and leaves the address at
N+16. This instruction takes about 2 microseconds.
XEROX GRAPHICS PRINTER SECTION 17
DATAO 440,
----
18 | X
19 | 1
20 | VIDEO
---- ↑
21 | |
22 | |
23 | |
---- |
24 | |
25 | |
26 | |
---- |
27 | |
28 | |
29 | |
---- |
30 | ↓
31 | VIDEO
32 | WIDTH
---- ↑
33 | |
34 | ↓
35 | WIDTH
----
This command loads WIDTH bits into the memory. All 12 VIDEO
bits are ored into a shift register and then shifted WIDTH times.
This is useful for overprinting characters. The address counter is
incremented by WIDTH. This instruction takes WIDTH*120 nanoseconds,
which is less than 1.5 microseonds, so I wouldn't worry about that
too much.
Bit 20 of the data goes into the first (leftmost) available
bit in the scan line buffer. The buffer pointer is advanced by
WIDTH.
XEROX GRAPHICS PRINTER SECTION 17
Program operation of the XGP
An operating sequence consists of the following commands:
;LOCATION 40+2*XGPCHN CONTAINS: JSR XGPCHL
XGPCHL: 0
CONSZ XGP,10
JRST XGPINT
JEN @XGPCHL
;HERE WHEN XGP MAKES A DONE INTERRUPT.
XGPINT: CONO XGP,160110!XGPCHN
;SET PI CHANNEL, CLEAR DONE,
;SET DONE ENABLE
CONSO XGP,100 ;TEST XGP OK
JRST XGPHNG ;DEVICE IS HUNG.
CONO XGP,140000 ;SET COLUMN REGISTER TO 0
CONO XGP,170004 ;SWAP BUFFERS
CONO XGP,140000 ;SET COLUMN REGISTER TO 0
.... ;COMPUTE NEXT SCAN LINE
;Turn on paper motion by
;CONO XGP,160130!XGPCHN
JEN @XGPCHL ;DISMISS INTERRUPT
At appropriate places, mark the paper to be cut.
Before sending data to the XGP it must be synchronized. This is
accomplished by switching buffers 4000 times.
Before sending data, turn on the paper motion. Paper must be run
for about 600 lines before sending data.
After turning paper off, the paper will continue to run for about
4200 lines. Cut marks should be made while the paper is stopping to
prevent getting long pages.
XEROX GRAPHICS PRINTER SECTION 17
Care and feeding of the XGP.
The normal condition of the XGP is indicated by the green
"ON" light and the orange "READY" light being on.
If all indicators are off, the XGP main power has been shut
off inside the cabinet, possibly for some reason.
If the red "OFF" light is on, push the ON light. This will
turn the XGP on, unless some abnormal condition remains, such as a
paper jam near the cutter.
If the orange "STANDBY" light is on, look inside the panel
above these indicators. The following is the normal state of the
indicators and switchs within:
Knobs: VERTICAL POSITION: Don't touch it!
TEST PATTERN: OFF
Lights that should be on:
All "POWER SUPPLIES" lights
(except 10kv and 2.5kv lights will
be off any time there is some other
problem.)
All "PROCESS INTERLOCK" lights
All "CONTROL LOGIC" (except IN SYNC).
Lights that should be off:
All "SUPERVISORY SIGNAL"
"FAULT"
"IN SYNC"
Certain conditions of the XGP are indicated by lights being OFF. (If
any of the conditions listed below occurs, the 10kv and 2.5kv power
supplies will shut off.)
FWT Filiment wait timer has not run long enough after
being turned on. Wait 2 minutes.
FUSER The fuser is not hot enough. If the XGP has just been
turned on, wait 5 minutes, otherwise, check the over-
temperature sensor.
WEB CLEAN
The drum cleaning web must be replaced.
PAPER OUT
Load more paper.
SWEEP PRESENT
The interface is not providing a sweep signal. The
connector may be unplugged or the interface turned
off.
The sequence "OFF, wait 10 seconds, ON, wait 30 seconds" may remedy
some other problems. This sequence should never be used while the
XGP is active.
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
This section gives the bits used for controlling the IBM
channel which in turn controls the IBM 3330 disk. This information is
for system programmers.
CONI 500,
These bits describe most of the current state of the channel.
BIT __ ___ FUNCTION
0 |___ unused
1 |___ NXM
2 __|___ Data chain error
3 |___ Select error
4 | Status address 0
5 __| Status address 1
6 | Status address 2
7 | Status address 3
8 __| Status address 4
9 | Status address 5
10 | Status address 6
11 __|___ Status address 7
12 |___ Disk parity error
13 |___ Core parity error
14 __|___ Idle state
15 |___ Request(RQ)
16 |___ Initial Select state(IS)
17 __|___ Trans state
18 |___ Parity error
19 |___ Command hold empty
20 __|___ Idle state
21 |___ Unusual end
22 |___ New status
23 __| Status register 0
24 | Status register 1
25 | Status register 2
26 __| Status register 3
27 | Status register 4
28 | Status register 5
29 __| Status register 6
30 |___ Status register 7
31 |___ PI Active
32 __|___ unused
33 |
34 | PI channel
35 __|___
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONO 500,
The bits transmitted by a CONO 500, enable interrupts from
various conditions and sets up the PI channel. For a description of
the bits see CONI 500.
BIT __ ___ FUNCTION
18 |___ Disk ∨ Core parity error
19 |___ Command hold empty
20 __|___ Idle
21 |___ Unusual end
22 |___ New status
23 __|___ Attention
24 |___ Status modifier
25 |___ Control unit end
26 __|___ Busy
27 |___ Channel end
28 |___ Device end
29 __|___ Unit check
30 |___ Unit exception
31 | unused
32 __|___ load PI from bits 33-35
33 |
34 | PI channel
35 __|___
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
DATAO 500,
A DATAO 500,X is used to load the negative word count and the
beginning memory address. Location X has the negative word count in
the left half and the MA in the right half. The word count is the
number of 36 bit words to be transfered when count bytes is not on in
the datao, otherwise it is the number of 8 bit bytes to be
transfered.
DATAI 504,
This instruction puts the current memory address into the
effective address (you do not get the word count).
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONI 504,
This gives you more information on the state of the
interface.
BIT __ ___ FUNCTION
18 |
19 |
20 __| unused
21 |
22 |___
23 __|___ ¬Opl in
24 |___ Data chaining
25 |___ WCMA hold loaded
26 __|___ Command hold loaded
27 |___ Idle state
28 |___ request
29 __|___ IS state
30 |___ Trans state
31 |___ Command hold empty
32 __|___ Command hold full
33 |___ OPL out
34 | unused
35 __|___
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONO 504,
This is the control CONO that sets and resets things.
BIT __ ___ FUNCTION
18 |
19 |
20 __| unused
21 |
22 |
23 __|___
24 |___ Clear Un End
25 |___ Reset memory multiplexer
26 __|___ Clear data chaining
27 |___ Clear active
28 |___ Clear new status
29 __|___ Power clear (not useful, takes about 3 seconds)
30 |___ Clear status register
31 |___ Reset command hold loaded
32 __|___ Set command hold loaded
33 |___ Set hold suppress and reset OPL out
34 |___ Reset OPL out
35 __|___ Reset channel
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
DATAO 504,
When executed, DATAO 504,X sets command hold loaded and loads
the command hold register from location X which has the following
format:
BIT __ ___ FUNCTION
0 |
1 |
2 __|
3 |
4 |
5 __|
6 | unused
7 |
8 __|
9 |
10 |
11 __|
12 |
13 |___ Data chaining
14 __| Address 0
15 | Address 1
16 | Address 2
17 __| Address 3
18 | Address 4
19 | Address 5
20 __| Address 6
21 |___ Address 7
22 |___ Set command hold requires memory transfer
23 __|___ 4 byte mode
24 |___ Count bytes
25 |___ Chaining
26 __|___ Skip mod on
27 |___ Skip mod off
28 | Command 0
29 __| Command 1
30 | Command 2
31 | Command 3
32 __| Command 4
33 | Command 5
34 | Command 6
35 __|___ Command 7
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONI 500,
Executing a CONI 500, allows you to see some of the status of
the channel.
BIT Number MEANING
1 200000 Non-existent memory. The channel was reading
from or writing into memory and no one
responded to the address in the MA register.
The address is illegal or a memory is hung.
2 100000 Data chain error. The current command
indicated data chaining and no word count, MA
had been loaded.
3 40000 Select error. The channel addressed a device
which did not respond to select out.
4-11 37700 Last address used in an initial select
sequence.(i.e. the address of the device it
is selecting).
12 40 Bit 18 is also set. Means parity error was
detected by the control unit.
13 20 Bit 18 is also set. Means parity error was in
main memory.
14 10 Idle state. The channel is not currently
processing any commands or doing any
transfers.
15 4 IS state. The channel is in the Initial
Select state. This means that the channel is
establishing contact with the device
addressed by bits 4-11.
16 2 Request. A device is requesting
selection. (i.e. it has status for the
channel.)
17 1 Trans state. Transfer is in progress between
the channel and the selected device.
18 400000 A parity error was detected by the interface
or the control unit.
19 200000 Command hold empty:
¬Command_hold_loaded ∨
Unusual end ∨
(¬WCMA_hold_loaded ∧
Command_hold_requires_memory_transfer.)
20 100000 Idle state. Same as bit 14.
21 40000 Unusual end. The channel has detected some
error condition(s). The following things can
cause unusual end:
1) Non-Ex Mem.
2) Select Error.
3) Busy
4) Unit Check.
5) Data Chain Error.
Unusual end can be cleared by CONO 504 if
only 3 or 4 are true.
Otherwise a reset is required.
22 20000 New status. The channel has status from a
device ready for you. No further status can
be accepted from a device until new status is
cleared(see CONO 504).
23 10000 Attention. This indicates some asynchronous
condition in the IO device. (Not used in 2314
or 3330)
24 4000 Status modifier. Is used to indicate special
status conditions.
25 2000 Control Unit End. Indicates that the control
unit is free after Control Unit Busy or that
an unusual condition was detected after
channel end but while still busy.
26 1000 Busy. The device is busy on your last command
unless accompanied by status modifier in
which case the control unit is busy.
27 400 Channel end. The control unit is finished but
not necessarily the device.
28 200 Device end. The IO device has completed the
last operation.
29 100 Unit check. Error conditions exist in the IO
device. More information is available by a
sense command.
30 40 Unit exception. Device dependent. Sometimes
used to indicate end of file.
31 20 PI active. Channel is requesting an interrupt.
33-35 7 PI channel.
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
Further description of device status byte bits 23-30 of coni 500 as
they pertain to the 3830 control unit, and 3330 disk drives
(attention is omitted for clarity):
|status| cu | | chan | dev | unit | unit |
| mod. | end | busy | end | end | check | xcptn | meaning
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| (x) | | | x | x | | | normal end
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | | channel done,
| | | | x | | | | device still busy
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | | device done,
| (x) | | | | x | | | after above
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| | | | x | x | x | | error end
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| | | | | x | x | | error end
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| x | | x | | | | | c.u. busy
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| | x | | | | | | c.u. end
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | | drive busy on
| | | x | | | | | last command
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| x | | | x | | x | | command retry
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| x | | | x | x | x | | command retry
|______|_____|______|______|_____|_______|_______|___________________
| | | | | | | |
| | | | | | | x | end of file
|______|_____|______|______|_____|_______|_______|___________________
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONO 504
Cono to set and reset things in the channel.
BIT Number MEANING
24 4000 Clear Unusual end. Will not clear if there is
a Non-Ex Mem., select error, or data chaining
error. Reset will always clear it however.
25 2000 Clear memory multiplexer. Will hang memory if
multiplexer is active.
26 1000 Clear data chaining. This must be done when
using data chaining and just before the last
WCMA is sent. Otherwise data chain error will
occur when the WCMA runs out.
27 400 Clear any interrupt request the channel is
now holding.
28 200 Clear the new status indication. Allows more
status to be accepted from an IO device.
29 100 Power clear. Implies reset, but clears more
things. (for adjusting delay only, takes
about 3 sec.)
30 40 Clear bits 23-30 of the CONI 500. Must be
done to stop interrupts if the channel is
enabled for any of the status conditions.
NOTE: due to race conditions you should not
send this bit with bit 28, Otherwise you may
lose status.
31 20 Resets the command hold loaded condition, but
does not clear the command. Command chaining
cannot take place unless command hold leaded
is true.
32 10 Set command hold loaded.
33 4 Set suppress out and reset OPL out. This
resets only the currently selected device.
34 2 Reset OPL out. This resets all devices
attached to the channel.
35 1 Reset the channel.(must sometimes be done
three times at spaced intervals to work.)
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
CONI 504
This indicates some of the state of the channel.
BIT NUMBER MEANING
23 10000 ¬Opl In. A control unit is currently attached
to the channel.
24 4000 Data chaining. This means that the next word
count, MA will be chained to the command.
25 2000 WCMA hold loaded. The next word count, MA is
ready. must be true for data chaining to
happen.
26 1000 Command hold loaded. The next command in the
chain is loaded.
27 400 Idle state. The channel is idle.
28 200 Request. The channel is receiving a request
from an IO device for some kind of service.
29 100 IS. The channel is in the initial select
sequence.
30 40 Trans. The selected IO device is in the
middle of a transfer (in or out).
31 20 Command hold empty. ¬Command hold full.
32 20 Command hold full:
Command hold loaded ∧
(WCMA hold loaded ∨
¬Command hold requires memory transfer.)
33 4 OPL out. Operational out. The channel is
indicating to all devices that it is ready.
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
DATAO 504
This puts the command in the command hold buffer, and sets
command hold full.
BIT NUMBER MEANING
13 20 Data chaining. This command will do data
chaining until this bit is reset.
14-21 17,,740000 Address. This is the number of the device
which you wish to give the command to.
22 20000 Set command hold requires memory transfer.
This indicates that the next command will
require a transfer to or from memory.
23 10000 4 byte mode. This indicates that data going
to and from memory is packed 4 bytes to a
word instead of 4 1/2 bytes to a word.(this
is described in detail on the next page.)
24 4000 Count bytes. This indicates that the word
count is really a byte count.
25 2000 Chaining. This indicates that the following
command should be chained to the current one.
26 1000 Skip mod on. The command in the command hold
buffer should be skipped if the status
modifier is on at the end of this command.
27 400 Skip mod off. Skip next command if status
modifier is off.
28-35 377 Command. The command to be sent to the
selected IO device.
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
4 BYTE MODE:
8 BIT BYTES ARE PACKED 4 TO A WORD AS FOLLOWS:
__________________________________________
| | | | | |
| BYTE 0 | BYTE 1 | BYTE 2 | BYTE 3 | |
|________|________|________|________|____|
0 7 8 15 16 23 24 31 32 35
__________________________________________
| | | | | |
| BYTE 4 | BYTE 5 | BYTE 6 | BYTE 7 | |
|________|________|________|________|____|
0 7 8 15 16 23 24 31 32 35
IF NOT IN 4 BYTE MODE BYTES ARE PACKED 4 1/2 BYTES PER WORD
AS FOLLOWS:
_____________________________________________
| | | | | BYTE 4 |
| BYTE 0 | BYTE 1 | BYTE 2 | BYTE 3 |BITS 0-3|
|________|________|________|________|________|
0 7 8 15 16 23 24 31 32 35
______________________________________________
| | | | | BYTE 4 |
| BYTE 5 | BYTE 6 | BYTE 7 | BYTE 8 |BITS 4-7|
|________|________|________|________|________|
0 7 8 15 16 23 24 31 32 35
THIS LATTER MODE IS GENERALLY USED ONLY FOR TRANSFER OF DATA TO AND
FROM THE 2314.
Command Chaining:
When command chaining is indicated the channel sets up
special conditions in the selected control unit. Error conditions
will arise if there is no command in the command hold buffer when
needed for chaining.
Data Chaining:
Indicates that another word count MA is in the WCMA hold
buffer for this command. If the WCMA hold buffer is not loaded a data
chaining error will occur. The method is to keep loading WCMA's when
WCMA hold loaded is false until the last WCMA, then clear the data
chaining bit (CONO 504) before loading the last WCMA.
* IBM BLOCK MULTIPLEX CHANNEL SECTION 18
PARTIAL DESCRIPTION OF THE OPERATION OF THE IBM 2314 DISK STORAGE
SYSTEM. WITH ADDITIONS FOR 3330.
Address bits in the datao 504 when used with 2314 or 3330:
Bits 14-18 device number 6 for 2314
14 for 3330
bits 19-21 logical pack #
COMMANDS:
THE 200 BIT ON IN THE COMMAND INDICATES AUTOMATIC HEAD SWITCHING WHEN
CHAINING COMMANDS.
The number of bytes normally transfered is given in the description
of the command. The number of bytes actually transfered depends on
the word count used in the datao to device 500. In most cases a word
count smaller than the one suggested will merely mean less data is
transfered, but some commands require exactly the right word count.
For read and write commands data is transfered until the count runs
out or the end of the data area is encountered.
SENSE COMMAND (004):
TRANSFERS 24 BYTES(3330) OF SENSE INFORMATION TO MEMORY.
MEANINGS OF THE BYTES ARE DESCRIBED IN THE IBM 3330 DIRECT
ACCESS STORAGE FACILITY MANUAL.
NO OP(003):
NO ACTION IS TAKEN. Should get channel end and device end
from the control unit.
RECALIBRATE(023):
CAUSES THE SPECIFIED MODULE (BITS 19-21) TO SEEK TO CYLINDER
0, HEAD 0 (SHOULD BE DONE AFTER SEEK CHECK).
SET FILE MASK(037):
ONE BYTE IS TRANSFERED FROM MEMORY TO THE 2314. IT SETS THE
FILE MASK TO BE USED FOR THE REST OF THE CURRENT COMMAND
CHAIN. THE BITS HAVE THE FOLLOWING MEANINGS:
BITS 0 & 1
PERMIT WRITE COMMANDS
00 ALL EXCEPT WRITE HOME ADDRESS
AND WRITE RECORD 0.
01 NONE(NO WRITING ALLOWED).
10 WRITE DATA OR WRITE KEY & DATA
11 ALL (necessary for formatting)
BIT 2 SHOULD BE ZERO
BITS 3 & 4
PERMIT SEEK COMMANDS
00 ALL.
01 SEEK CYLINDER OR SEEK HEAD.
10 SEEK HEAD
11 NONE
BITS 5-7 SHOULD BE ZERO (2314)
BIT 5 (3330) =1 PERMIT DIAGNOSTIC WRITE COMMANDS
BIT 6 (3330) NOT USED, SHOULD BE 0
BIT 7 (3330) =1 PCI FETCH MODE (UNIT CHECK IF COMMAND RETRY
USED TO RECOVER FROM UNCORRECTABLE DATA ERROR).
SEEK(007):
SEEK CYLINDER(013):
SEEK HEAD(033):
6 BYTES ARE READ FROM MEMORY. BYTES 0-2 & 4 SHOULD CONTAIN 0.
BYTE 3 SHOULD CONTAIN A LEGAL CYLINDER NUMBER AND BYTE 5
SHOULD CONTAIN A LEGAL HEAD NUMBER.
SEARCH HOME ADDRESS EQUAL(071 OR 271):
COMPARE THE HOME ADDRESS INFO ON THE TRACK WITH THE FIRST 4
BYTES FROM MEMORY TO SEE IF THEY ARE EQUAL. THE STATUS
MODIFIER IS SET IF THE COMPARE IS EQUAL.
SEARCH IDENTIFIER(XX1):
5 BYTES FROM MEMORY ARE COMPARED WITH BYTES 1-5 OF THE COUNT
AREA OF THE NEXT RECORD ENCOUNTERED.
SEARCH ID EQUAL(061 OR 261):
COMPARE FOR ALL BYTES EQUAL.
SEARCH ID HIGH(121 OR 321):
COMPARE FIRST UNEQUAL BYTE ON DISK TO SEE IF IT IS HIGHER
THAN THE ONE FROM MEMORY.
SEARCH ID HIGH OR EQUAL(161 OR 361):
COMPARE EQUAL OR HIGH.
THE STATUS MODIFIER IS SET IF THE ENDING CONDITION IS TRUE.
SEARCH KEY(XX1):
COMPARE BYTES FROM MEMORY WITH THE NEXT KEY AREA ENCOUNTERED.
SAME TESTS AS FOR SEARCH IDENTIFIER.
SEARCH KEY EQUAL(051 OR 251).
SEARCH KEY HIGH(111 OR 311).
SEARCH KEY HIGH OR EQUAL(151 OR 351).
STATUS MODIFIER IS SET ON TRUE ENDING CONDITIONS.
SEARCH KEY AND DATA EQUAL(055 OR 255).
SEARCH KEY AND DATA HIGH(115 OR 315).
SEARCH KEY AND DATA HIGH OR EQUAL(155 OR 355).
ANALOGOUS TO SEARCH KEY.
SPACE COUNT(017):
3 BYTES IN MEMORY INDICATE KEY LENGTH(BYTE 0) AND DATA LENGTH
(BYTES 1 & 2) IN ORDER TO SKIP OVER BAD AREAS ON THE TRACK.
READ HOME ADDRESS(032 OR 232):
TRANSFERS 5 BYTES OF INFO TO MEMORY FROM THE HOME ADDRESS
AREA ON THE TRACK. BYTE 0 FLAG BYTE, BYTES 1&2 CYLINDER NUM.,
BYTES 3&4 HEAD NUMBER.
READ COUNT(022 OR 222):
READS BYTES 1-8 OF THE COUNT AREA FOLLOWING THE NEXT ADDRESS
MARKER INTO MEMORY.
READ TRACK DESCRIPTOR RECORD 0(026 OR 226):
READS BYTES FROM THE COUNT AREA (BYTES 1-8), THE KEY AREA AND
THE DATA AREA INTO MEMORY UNTIL THE WORD COUNT IS EXHAUSTED.
READ DATA(006 OR 206):
READS DATA FROM A GIVEN RECORD. SEE MANUAL TO DETERMINE WHICH
RECORD WILL BE READ.
READ KEY AND DATA(016 OR 216):
SAME AS READ DATA EXCEPT THAT THE KEY AND DATA AREAS ARE READ.
READ COUNT, KEY AND DATA(036 OR 236):
SAME AS READ DATA EXCEPT THAT BYTES 1-8 OF THE COUNT AREA,
THE KEY AREA, AND THE DATA AREA ARE READ.
READ INITIAL PROGRAM LOAD(002):
SEEKS CYLINDER 0 HEAD 0 OF THE SELECTED MODULE THEN READS
RECORD 1.
WRITE HOME ADDRESS(031):
5 BYTES OF DATA ARE TRANSFERED FROM MEMORY TO BYTES 1-5 OF
THE HOME ADDRESS AREA OF THE CURRENT TRACK.
WRITE TRACK DESCRIPTOR RECORD(025):
DATA IS TRANSFERED FROM MAIN MEMORY TO RECORD ZERO. THE COUNT
AREA (BYTES 1-8), KEY AREA, AND THE DATA AREA.
WRITE DATA(005).
WRITE KEY AND DATA(015).
WRITE COUNT KEY AND DATA(035).
ANALOGOUS TO WRITE TRACK DESCRIPTOR.
THE FOLLOWING APPLY ONLY TO 3330:
SET SECTOR:
ONE BYTE IS TRANSFERED.
BYTE = 0-127 STORAGE CONTROL ATTEMPTS RECONNECTION JUST
BEFORE REACHING THE DESIGNATED SECTOR.
BYTE = 128-254 ILLEGAL, CAUSES UNIT CHECK.
BYTE = 255 FLUSH PREVIOUS SET SECTOR (STORAGE CONTROL
WILL NOT ATTEMPT RECONNECTION).
RESTORE:
EQUIVALENT TO NO-OP.
DIAGNOSTIC LOAD:
TAKES ONE BYTE, AN ADDRESS IN THE CONTROL UNITS READ ONLY
STORE. 512 BYTES ARE TRANSFERED FROM THERE TO THE CONTROL
BUFFER. THESE MAY BE READ BY A SUBSEQUENT READ DIAGNOSTIC
STATUS 1 COMMAND.
DIAGNOSTIC WRITE:
TRANSFERS 512 BYTES FROM MAIN MEMORY TO CONTROL BUFFER AND
EXECUTES THE TEST, STORING A 16 BYTE ERROR CODE MESSAGE UPON
TERMINATION. THE 16 BYTE ERROR CODE MESSAGE CAN BE READ BY A
SUBSEQUENT READ DIAGNOSTIC STATUS 1 COMMAND. IF COUNT IS LESS
THAN 512, UNIT CHECK IS GENERATED.
READ SECTOR:
ONE BYTE IS TRANSFERED, THE CURRENT ROTATIONAL POSITION.
READ AND RESET BUFFERED LOG:
TRANSFER 24 BYTES OF USAGE OR ERROR INFORMATION FROM THE
STORAGE CONTROL.
READ DIAGNOSTIC STATUS 1:
FOLLOWING DIAGNOSTIC WRITE COMMAND; TRANSFERS 16 BYTE ERROR
CODE MESSAGE FROM CONTROL BUFFER TO MAIN STORAGE.
FOLLOWING DIAGNOSTIC LOAD COMMAND; TRANSFERS 512 BYTES FROM CONTROL
BUFFER (DATA READ FROM ROM) TO MAIN MEMORY.
* TELEPHONE PAGING SYSTEM KLUDGE SECTION 19
Device 370 on the PDP-10 TTL IO BUS extension is the paging system
interrupt kludge (PK in the system). It is not to be confused with
the BBN Paging System which is a kludge, but traps rather than
interrupting. The PK is connected to the telephone paging system and
interrupts the time- sharing system whenever a page begins and again
whenever it ends. The CONO and CONI bits are as follows:
CONO PK,
BIT VALUE FUNCTION
31 20 Clear interrupt
32 10 Set interrupt
33-35 7 PIA
CONI PK,
BIT VALUE FUNCTION
31 20 A page is currently in progress
32 10 The PK is trying to interrupt (i.e. done)
33-35 7 PIA
* VODER INTERFACE SECTION 20
This is a description of the VODER, a speech synthesizer made
by the Votrax division of the Federal Screw Works, and its interface
to the PDP-10. The VODER takes a string of 8 bit characters, each
representing a phoneme. There are 61 phonemes and Two lengths of
pause, each with four values of inflection, and a null (making 256
possible characters).
The interface has 2 distinct modes, LOAD, and GO. In load
mode, up to 80 phoneme characters are loaded into an internal buffer,
four characters at a time. Then, the GO command is issued which
causes the VODER to output its current buffer-full. When it is done
(which may take quite a long time) it will transfer itself back into
LOAD mode and interrupt on the selected PI channel. If a NULL (077)
is encountered in the output stream, the output is halted and returns
to LOAD mode. A GO command will cause it to proceed through the
buffer.
The Voder is device 360.
CONO/CONI VOD,
____
|18
|19
____|20
|21
|22
____|23
|24
|25
____|26
|27
|28
____|29
|30
|31 GO/BUSY
____|32 CLEAR INTERRUPT/INTERRUPTING
|33 PI33
|34 PI34
____|35 PI35
In order to clear the VODER of residual data after powering
up, a CONO VOD,10, then a CONO VOD,20 must be executed. Then wait
for BUSY to go away. Finally, clear INTERRUPTING.
* VODER INTERFACE SECTION 20
A DATAO to the VODER will load four characters into the 80
character buffer. If the VODER is in GO mode (BUSY) characters will
be ignored. Characters that do not have the VALID bit on will be
ignored.
DATAO VOD,X
X: ____ _____ ____
|0 C __VALID
|1 H
____|2 A
|3 R
|4 A 1
____|5 C
|6 T
|7 E
____|8 _____R____
|9 C __VALID
|10 H
____|11 A
|12 R
|13 A 2
____|14 C
|15 T
|16 E
____|17_____R____
|18 C __VALID
|19 H
____|20 A
|21 R
|22 A 3
____|23 C
|24 T
|25 E
____|26_____R____
|27 C __VALID
|28 H
____|29 A
|30 R
|31 A 4
____|32 C
|33 T
|34 E
____|35_____R____
The sequence for operation of the VODER is as follows. Check
the BUSY bit with a CONI. Then DATAO ≤ 80 valid characters. Now CONO
the GO bit and a PI channel. This causes the VODER to output its
buffer-full. The device will now show BUSY for a while and then,
when it is done speaking, remove BUSY and interrupt. A CONO with the
CLR INT bit on will clear the interrupt. If more than 80 valid
characters are sent, the last 80 will be used and the first ones
forgotten.
* VODER INTERFACE SECTION 20
APPENDIX
Here is a list of all the phonemes, their codes, and the
approximate sound of each. The inflection is added as the two low
order bits in each 8 bit character. Highest pitch inflection is 000,
next is 001 (normal), then 002, and the lowest pitch is 003.
PHONEME OCTAL AS IN
PA0 300 WORD PAUSE
PA1 174 COMMA PAUSE
A 004 EIGHT
A1 140 NAME
A2 240 RATE
AE 164 CAT
AE1 364 ALTITUDE
AH 044 NINE
AH1 250 HOUR
AH2 020 FLIGHT
AW 274 LAW
AW1 310 COST
AW2 014 POT
AY 204 WAVE
B 160 BED
CH 010 CHAIR
D 170 EDGE
DT 040 NOTIFY
E 064 KEEPER
E1 074 HERE
EH 334 TEN
EH1 100 TED
EH2 200 ED
EH3 000 TELL
ER 134 WEATHER
F 270 FOR
G 070 GET
H 330 HELLO
I 344 SIX
I1 320 WIND
I2 120 ALTITUDE
I3 220 EXECUTE
IU 154 TWO
J 130 EDGE
K 230 CAME
L 030 HELLO
M 060 MILE
N 260 NINE
NG 050 RING
O 144 NO
O1 254 HOLD
O2 054 OUT
OO 350 BUSH
OO1 150 ERROR
P 244 PENNY
R 324 THREE
S 370 SIX
SH 210 SHOW
T 124 TEN
TH 234 THREE
THV 034 THEN
U 024 LOSER
U1 354 EXECUTE
UH 314 UP
UH1 114 OBSERVE
UH2 214 KNOWN
UH3 304 WHEELS
V 360 SEVEN
W 264 WON
Y 224 SIXTY
Y1 104 YES
Z 110 ZERO
ZH 340 AZURE
NULL 374 DATA STOP
AUTO DIALER SECTION 21
The automatic dialer allows the computer to dial the 493-5506
dataphone. The number is dialed by first doing a CONI to find out if
the phone is busy, then doing a CONO to set up things, and then a
DATAO of the number. The dialer interface will interupt when it
thinks something happened that you should know about, such as the
number you dialed answered, or it didn't. The format of the
instructions is as follows:
CONI 374,[x] * = causes interrupt
x: |18
|19
____|20
|21
|22
____|23
* |24 DSS←1 Data set answered or voice call
* |25 DSS←0 Data set disconnect
____|26 DLO Busy
* |27 ¬ACR Data phone not hung (OK)
|28 DSS Data set connected
____|29 VOICE
* |30 ¬PWI Power fail
|31 INTERRUPT
____|32 INTERRUPT ENABLE
|33 PI33
|34 PI34
____|35 PI35
CONO 374,x
x: |18
|19 A FIRST
____|20 R DIGIT
|21 E ____
|22 A
____|23 SECOND
|24 DIGIT
|25 C ____
____|26 O
|27 D THIRD
|28 E DIGIT
____|29 ________
|30 CLEAR INTERRUPT [DILCLR]
|31 HANG UP [DILHNG]
____|32 INTERRUPT ENABLE [DILENB]
|33 PI33 [DILCHN]
|34 PI34
____|35 PI35
AUTO DIALER SECTION 21
DATAO 430,[x]
____
x: |0
|1
____|2
|3
|4
____|5
|6 AREA
|7 VOICE
____|8
|9 N FIRST
|10 U DIGIT
____|11 M ____
|12 B
|13 E SECOND
____|14 R DIGIT
|15 ____
|16
____|17 THIRD
|18 T DIGIT
|19 O ____
____|20
|21 FOURTH
|22 DIGIT
____|23 B ____
|24 E
|25 FIFTH
____|26 DIGIT
|27 ____
|28 D
____|29 I SIXTH
|30 A DIGIT
|31 L ____
____|32 E
|33 D SEVENTH
|34 DIGIT
____|35 ________
AUTO DIALER SECTION 21
The following is a brief description of what each of the bits means.
DSS DATA SET STATUS
When this bit is on, it means that you have reached a
Dataphone and are connected to it.
DSS←1 DATA SET STATUS went on.
This means a Dataphone answered. This bit also comes on
immediately after a VOICE call has finished dialing.
DSS←0 DATA SET STATUS went off.
This means the Dataphone you called hung up. You should do
likewise.
DLO DATA LINE OCCUPIED
The dialer or its Dataphone is being used.
¬ACR NOT ABANDON CALL AND RETRY
After the number is dialed, if a Dataphone has not answered
within 15 seconds, this bit goes off. It is a suggestion
that you hang up and try again later. It has no effect on
the call.
VOICE VOICE MODE
When this bit is set, the dialer will dial the call and then
transfer the line to the A/D and D/A converters.
¬PWI NOT POWER INDICATION
Bit is on when there is no power to the dialer. Good for
disabling outgoing calls.
HANG UP
Sure enough, it hangs up a dialer initiated call.
INTERRUPT
Dialer is interrupting for some reason. Possible reasons are
DSS←1, DSS←0, ACR, attempting to dial with DLO, ¬PWI.
CLEAR INTERRUPT
Clears interrupt. An interrupt will occur when there is any
significant change in status.
INTERRUPT ENABLE
Enables dialer to interrupt when interrupt bit is on.
PI33-PI35
PI channel
AREA
This bit requires an Area Code to be dialed. Calls to the
415 dialing area must not have an Area Code.
PDP-10 TO PDP-11 INTERFACE SECTION 22
PDP-10 TO PDP-11 INTERFACE (PROGRAMMER'S-EYE VIEW)
The 10/11 interface is a connected to the PDP10's I/O Bus and to the
UNIBUS of the hand/eye PDP11/45. It makes NPR (non-processor) requests
on the UNIBUS for reading and writing of memory and PDP11 I/O registers.
(The PDP11's accumulators cannot be referenced in this way.) PDP11 data
is packed into 36 bit words for transmission the the PDP10 over the I/O
Bus.
PDP-10 TO PDP-11 INTERFACE SECTION 22
The UNIBUS TRANSFER BOX
This box contains a 32-bit data buffer register (two PDP-11 words),
a 17-bit UNIBUS address register, and 19 bits of mode control and
status information.
DATA BUFFER REGISTER (DATAI/DATAO)
For output from the 10, this register holds one or two 16-bit PDP-11
words until the UNIBUS cycles for writing them become available.
For input, it assembles one or two 16-bit words and holds them until
the 10 can read the result. In all modes that transfer two PDP-11
words, the leftmost PDP-10 bits correspond to the lower address
on the Unibus. The gating between this register and the I/O bus can
follow several different patterns under control of the mode bits:
Mode 0 (single word): one PDP-10 word holds one PDP-11 word in its
low-order 16 bits. On input to the 10, the high-order 20 bits may
be set either to 0 or to the sign of the 16 data bits.
Mode 1 (halfword): one PDP-10 word holds two PDP-11 words, each
right-adjusted in an 18-bit halfword. On input, the high-order two
bits of each halfword may be set either to 0 or to the sign of the
data in the halfword.
Mode 2 (integer): one PDP-10 word holds two PDP-11 words as a 32-bit
integer right-adjusted in the 36 bits. On input, the high-order 4
bits may be set either to 0 or to the sign of the data.
Mode 3 (fraction or byte): one PDP-10 word holds two PDP-11 words as
a 32-bit number left-adjusted in 36 bits. On input, the low-order 4
bits are set to 0.
PDP-10 TO PDP-11 INTERFACE SECTION 22
CONI BITS FROM THE TRANSFER BOX
Bit 0 (SPINT) special interrupt (see bits 18-23 for reason)
Bits 1-17 are the current contents of the UNIBUS address register.
This register is incremented by 1 for each word transferred. The 17
bits of this register become an 18-bit UNIBUS address by having a
low-order zero appended. Thus, this register addresses 16-bit
PDP-11 words.
Bits 18-23 are status information associated with the special PI
channel interrupt:
400000 Bit 18 (IREQ) the interrupt was requested by program in the
11.
200000 Bit 19 (HALTED) the 11 is halted.
100000 Bit 20 (NXM) there was no response to the UNIBUS address.
40000 Bit 21 (BUSTO) unable to gain control of the UNIBUS.
20000 Bit 22 (BUSNIT) a UNIBUS INIT (reset) is going on, and that's
why your attempted transfer failed. Try again 10
milliseconds from now.
10000 Bit 23 (PARBAD) bad parity.
Bits 24-25 give the status of the current transfer:
4000 Bit 24 (BUSY) transfer in progress.
2000 Bit 25 (DONE) transfer complete. Causes a normal PI
interrupt.
Bits 26-35 are control and status bits set by the last CONO.
1000 Bit 26 (GRAB)
400 Bit 27 (SEXT)
300 Bits 28-29 (MODE)
Bits 30-32 (PI2 - Special interrupts)
Bits 33-35 (PI1 - Data interrupts)
PDP-10 TO PDP-11 INTERFACE SECTION 22
CONO BITS TO THE TRANSFER BOX
If Bit 18 is 0, the rest of the bits are control information:
200000 Bit 19 (PWRFAIL) Simulate power fail on the 11. Useful for
when the 11 is halted. Traps thru 24. (beware - it happens
twice!)
100000 Bit 20 (RESET) resets interface
40000 Bit 21 (CLRINT) clears special PI interrupt and interrupting
conditions (NXM, BUSTO, IREQ, HALT, PARHI, PARLO)
20000 Bit 22 (IGNPAR) don't check for parity errors on input
(still generates correct parity on output)
10000 Bit 23 (STOP) Clears BUSY and DONE, stops the transfers,
releases the UNIBUS.
4000 Bit 24 (GO) on output, clears BUSY and sets DONE (prepare
to send the first word). On input, sets BUSY and clears
DONE (start reading from the UNIBUS).
2000 Bit 25 (R/W) 0 means input to the 10, 1 means output.
1000 Bit 26 (GRAB) if on, the transfer box holds on to the UNIBUS
continuously. If off, it relinquishes the bus between
transfers.
400 Bit 27 (SEXT) on input, 0 means fill high-order data bits
with 0's, 1 means extend the sign of the data.
300 Bits 28-29 (MODE) give the data-packing mode (see
description of data buffer).
Bits 30-32 (PI2) PI channel assignment for special interrupts.
Bits 33-35 (PI1) PI channel assignment for DONE-bit
interrupts (BLKI/BLKO data transfers).
If Bit 18 is 1, the UNIBUS address register is loaded from bits 19-35.
PDP-10 TO PDP-11 INTERFACE SECTION 22
THINGS TO WATCH OUT FOR
Never do a DATAI, DATAO, or CONO when the interface is BUSY. Always
wait for DONE to come true or for BUSY to clear (both bits can be
CONIed and DONE causes an interrupt) The only exception to this is
when a special PI interrupt occurs (or if the special PI interrupt
bit comes on). In this case both BUSY and DONE will be cleared and
the reason for the interrupt may be determined from CONI bits 18-23.
You must clear the interrupt condition (with a CONO CLRINT) unless
you want it to interrupt right back when you dismiss on the special
PI channel. CONI bits 18-23 will be valid until a CONO CLRINT is
executed. The Unibus address register is usually left pointing to
the word after the last one transferred (i.e. it is incremented after
the transfer is complete). However, if an error condition (NXM,
BUSTO OR PARBAD) should occur, the Unibus address register will not
be incremented and will point at the next word that must be
transfered (i.e. the one that lost). In fact all cycles are stopped
on such an error and therefore it would be meaningless to do a DATAI
(if you happened to be doing input) even if the left halfword was
read successfully.
Note well: If you read the last valid core location, it will try to
go on and read the next address after that, thereby getting NXM.
This can be avoided by giving a CONO that changes the address to
something that won't get NXM just before executing the DATAI that
reads the last address.
RESETTING THE WORLD SECTION 23
This section describes the methods of resetting the various
devices that can get hung by mishaps of one kind or another. If the
expected thing does not happen when these instructions are followed
or something occurs that you don't understand, contact someone who
can figure it out.
DEC CORE MEMORIES
A DEC core memory is hung if, when both processors are
stopped, one of the following conditions is true:
"AW RQ" light is off.
"STOP" light is on.
"SYNC" light is on.
"RESTART" light is on.
any "ACTIVE" light is on.
To reset the memory, open the doors below the light panel
and push the "RESET" button (about chest high) while pushing the
"RESTART" button on the light panel. The only control lights that
should be on after resetting are "POWER" and "AW RQ". While you are
at it, check to see that the "RUN-MAINT" switch (about chest high)
is in the "RUN" position.
AMPEX CORE MEMORY
An AMPEX core memory is hung if its "UA" light is not on
when the processors are stopped. To reset, open the left-hand door
and push the black "CLEAR" button on the box at the bottom. If it
looks like the memory power is off to the , and the "CLEAR" button
doesn't help, the small switch "DC POWER" may have tripped to the
"OFF" position. It should be put in the "ON" position.
The Ampex interface (located between the two Ampex core
memories) will probably need to be reset if either of the memories
needed it. Simply push the white "RESET" button in the middle of
the light panel. When the interface is reset, the leftmost light of
each group, "EN", should be on.
NEW AMPEX CORE MEMORY
A NEW AMPEX core memory is hung if its "UA" light is off.
The core memories must be reset in pairs. Push the blue-green reset
button on units 0 and 1 (or 2 and 3) simultaneously.
RESETTING THE WORLD SECTION 23
PDP-6
The PDP-6 if it is running properly should have 5 in both
its PC and MA most of the time. If this is not true, put 204 in the
address switches, push stop, reset, and then start. If this doesn't
work try the section on the PDP-6 fast memory and then proceed as
above. If you still don't win, reload the system.
PDP-6 PARITY BOX
The PDP-6 parity box is located at the end of the row of DEC
memories nearest the PDP-6 console. If the "ERROR" light is on the
box has a condition that can be reset, but it really isn't necessary
unless the PDP-6 is hung. To clear the error, push the "CLEAR ERROR"
button on the light panel. If the switch "STOP" is in the up
position, and "ERROR" is on and the PDP-6 seems to be hung, push the
"RESTART" button. Do not push the "RESTART" button or change the
position of the "STOP" switch when the PDP-6 is running.
PDP-6 FAST MEMORY
The PDP-6 fast memory is located at the end of the PDP-6
console group of cabinets nearest the rest of the DEC memories. The
techniques for resetting it are the same as for the DEC core memories
with the following exceptions: The P0 "ACTIVE " light may be on and
the "RESET" button is about waist high and unlabeled.
RESETTING THE WORLD SECTION 23
III DISPLAY PROCESSOR
The III display processor is the light green cabinet on the
Ampex memory side of the computer complex. Open the doors on the
right side to see the lights. The processor needs to be reset if the
"NOT RUNNING" light is off and the processor is obviously not doing
anything. To reset, open the left-hand doors and push the white
"CLR" button at the extreme left side.
LINE PRINTER
The line printer will appear to be hung if the "START" light
is not on. This condition can be caused by many things, the most
common of which is someone forgetting to push "START" after removing
his listing. If this light is out try pushing it to see what
happens. If the light goes on, you are in the money. If it
doesn't, or if "STOP" and "START" are on at the same time, check that
the lights "LOW PAPER ALERT", "NO PAPER", "ALARM STATUS", "YOKE
OPEN", or "MANUAL PRINT" are all off. If "LOW PAPER ALERT" or "NO
PAPER" light is on, printer is probably out of paper. Reload the
paper supply. If "MANUAL PRINT" light is on, try pressing that button
and then "START". If that doesn't work, turn printer off by pressing
"OFF" button and wait until it lights up. Then press the "ON" button
and wait until it lights up. You should now be able to press
"START". If the "YOKE OPEN" light is on, open the cover of the
printer and hold the switches "OPEN-CLOSE" on both sides of the
printer mechanism (about waist high) in the "CLOSE" position until
the "YOKE OPEN" light goes out. If "ALARM STATUS" is on at any time
other than just after pushing "ON", something serious is wrong and
the appropriate hardware person should be contacted.
RESETTING THE WORLD SECTION 23
MAGNETIC TAPE DRIVES
The mag-tape drives can be set to funny states by pushing
buttons when no tape is loaded or if the drive misses or invents a
load or end point marker. The drives sometimes get into "skip to end
of tape" mode, which means it just keeps spacing until it runs of the
end of the reel. To reset any of these conditions, open the doors
under the drive and push the brass "CLEAR" button and all should be
fine.
DATA DISC
If you think data disc should be doing something and it isn't,
first check your program for illegal addresses. If that is all right,
push the black button labeled TRST on the front panel of the bay. If
it still doesn't run check your program again.
RESETTING THE WORLD SECTION 23
IBM 3330 DISC-PACK DRIVE
The IBM 3330 can have several things go wrong with it. The
most obvious thing is that one of the drives becomes "not ready" as
indicated by the green light corresponding to a pack in use not being
on.
The bulb can be checked by removing the plastic frob and
if the lamp is good, it should be glowing dimly. If this is the
case, try pulling out the number plug and pushing it back in again.
If this doesn't work, try turning the drive off and then back on
again. The drive should come ready within about 60 seconds. If all
these things fail, change pack to a drive not in use and swap the
number plugs.
The other most common failure is that the controller gets hung. To
find out about this, open the red doors at the front of the
controller (at the end of the PDP-10 great wall). Then swing the bay
of electronics out (releasing the catch at the left) and look at the
lights on the top of the swinging part. They should look like this:
ADDRESS/CHECK/PROGRAM DISPLAY
O O ⊗ ⊗ ⊗ O O O O O O O O O O ⊗ O O
REGISTER/STORAGE DISPLAY
O O O O O O O O O
⊗ = off; O = on;
If it doesn't look that way, stop computer, turn switch on right end
of panel to CE, actuate "RESET" switch (at right end of panel), frob
"IMPL" switch at left. Turn right switch back to NORMAL. There
whould now be a series of whirrs clicks and other such noises which
will quit after a while. Lights should now look like the above
picture. If they arn't, try turning power off (switch on right of
panel), witing 30 seconds, and turning it back on. It should then go
through its load sequence and start up. If they still arn't righta
you are in trouble so get someone who knows what they are doing.
RELOADING THE SYSTEM SECTION 24
RELOADING FROM THE LIBRASCOPE.
First push the stop switches on both the PDP-10 and PDP-6.
Now load the shiny blue "paper" tape loop into the tape reader on the
PDP-10. On the 10, push RESET, then READ-IN. The tape should read
for a while and then stop. If the tape stops and the teletype types
STANFORD ..... , then you are winning so go to the section called
WINNING, later on in this document. If the teletype types nothing,
look at Librascope. If it has no red lights on, check condition of
memories and try again. If it does, push RESET then CONTINUE. If
it does the same thing, you will have to load from Dectape.
RELOADING FROM DECTAPE
Load the tape "RIM 128K TENDUMP" into the tape reader. Push
RESET, READ-IN. The tape will read in and the teletype will go
"chunk". Find the dectape "SYSTEM TAPE" (it is usually on a drive, if
not, mount it) and remember the drive number. Then type n<alt> where
n is the drive number. Now type L<alt>S<CR>. The tape will spin and
then the teletype will go "chunk". Type 206<alt> then G<alt> (if
Librascope is down substitute 200 for 206). If it types STANFORD...
you are winning so go to WINNING. Otherwise, you are losing. Look
at Librascope for red lights. If there are some, push "RESET and then
CONTINUE". If not, do this:
1. Turn DOWN the switch labeled FM ENB on the panel on the left
above the console switches on the 10.
2. Set address switches (upper right bank of 18 console
switches) to zeroes.
3. Push "DEPOSIT THIS"
4. Push "DEPOSIT NEXT" three times.
5. Return FM ENB switch to original position.
6. Push "CONTINUE".
If the bell rings again, start over. If you get STANFORD...,
go to WINNING. If you really can't figure it out, call someone.
WINNING
If you get here, the teletype has typed STANFORD and then a
bunch of other shit the last of which may be "...AT 204 OR TYPE
<CR>." If so, go to the PDP-6 console and push STOP and then RESET.
Set the address switches at 204 (↓↓↓ ↓↓↓ ↓↓↓ ↓↑↓ ↓↓↓ ↑↓↓) and then
push START. If the PDP-10 types "DO YOU WANT TO REFRESH THE DISC?" (I
hope it doesn't) TYPE "N"!!!!! The teletype may now ask you to type
the date and time. Follow each answer with a <cr>. The system will
now either come up, or it won't. If it doesn't, the light "MEMORY
STOP" on the console may be on. If it isn't, you lose - go back to
the beginning. If it is, check that all memories are available and
start over. If you are trying to put up a system with less than a
full house of core, push CONTINUE and the system should come up. In
all cases, pay attention to what the console teletype tells you to do
and follow instructions.
RESETTING THE CLOCK
If you were requested to type the date and time when
reloading, the clock probably needs to be reset so that the dates of
your files will be correct. This takes two people. First log in at a
III console and type R DPYCLK. You should get a nice picture of a
clock and an indication of what day the clock thinks it is. Now, find
the clock. Start facing the PDP-6 console, turn right and go until
you can go left. Go left and then left again immediately. You should
be facing a rack of electronics with lots of messy wiring. About
shoulder height you will see a blue panel labeled "PETIT CROCK".
Turn off the switch labeled "RUN". Press all the 0 buttons in turn
starting from right to left. Now start toggling the rightmost two
switches push one then the other then the first then the...) until
the minutes on the display show about five minutes later than it is.
Then toggle the low order hour bit to the correct hour, and so on
until the clock is right. Then when the time is what the display
says it is, push the three lower reset buttons, and turn the RUN
switch back on and off you go.
GOOD LUCK!!!